Advanced Micro Devices Corporation

Other

Cypress Semiconductor Corporation

Spansion Llc.

David Michael Rogers

Mark T Ramsbey

Michael Allen Van Buskirk

Mimi Xuefeng Qian

Hidehiko Shiraiwa

Narbeh Derhacobian

Ravi S Sunkavalli

Jean Y Yang

Janet S Wang

Mark W Randolph

Yider Wu

Ravindra Manohar Kapre

Sungkwon Lee

Yan Yi

Timothy John Williams

Hiroyuki Kinoshita

Wei Zheng

Yi He

Tazrien Kamal

Eric N Mann

Toru Miyamae

Michael A VanBuskirk

Eric Lee Swindlehurst

Roger Tsao

Dung Ho

Mimi Xuefeng Zhao Qian

Kwadwo A Appiah

Boo Chin-Hua

Ryuta Nagai

Darlene G Hamilton

Timothy J Thurgate

Steven W Longcor

Kuang-Yeh Chang

Hsingya Arthur Wang

Michael David Fliesler

Fatima Bathul

Murtuza Lilamwala

Myeongseok Lee

Ian Morgan

Jih-Chang Lien

Ou Li

Huazhe Cao

Paohua Kuo

Henry H Yuan

Ken Tanpairoj

Ravi Sunkavalli

Janet Wang

An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

ESD protection circuit

A system and method for combining positive and negative voltage electrostatic discharge (ESD) protection into a clamp that uses cascoded circuitry, including detecting, by an electrostatic discharge protection system, a voltage pulse on an input pin of an integrated circuit (IC) controller, the IC controller coupled between a power supply node and a ground supply node; determining, by the ESD protection circuit, an ESD event on the input pin based on the voltage detected on the input pin; and/or controlling, by the ESD protection circuit during the ESD event, one or more clamps to transport the voltage pulse from the input pin of the IC controller to the power supply node.

Combined positive and negative voltage electrostatic discharge (ESD) protection clamp with cascoded circuitry

A semiconductor device () for improved charge dissipation protection includes a substrate (), a layer of semiconductive or conductive material (), one or more thin film devices () and a charge passage device (). The thin film devices () are connected to the semiconductive or conductive layer () and the charge passage device () is coupled to the thin film devices () and to the substrate () and provides a connection from the thin film devices () to the substrate () to dissipate charge from the semiconductive/conductive layer () to the substrate ().

Method and apparatus for protection against process-induced charging

A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.

Reduced state quadbit

A characterization method for a device under test includes applying a bias voltage to a test circuit. The test circuit includes a first transistor coupled to the device under test, a second transistor coupled to the device under test and to the first transistor. A third transistor is coupled to a dummy device, a fourth transistor is coupled to the dummy device and to the third transistor. The transistors are of a common type. The characterization method further includes applying non-overlapping clocking signals to transistors of the test circuit to produce test signals for application to the device under test and detecting a current in one or more transistors from the device under test. The bias voltage is further varied to characterize the device under test.

Clocked based method and devices for measuring voltage-variable capacitances and other on-chip parameters

An ESD protection device is provided for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply V and a second power supply V . An input protection device is also provided which is formed from a diode coupled between an input pad and the first power supply and a second diode coupled between the input pad and a second power supply. The diodes have an adjusted reverse breakdown voltage that is higher than the voltage supply V used to power the peripheral circuitry that drives circuitry within a core of the integrated circuit. The adjusted reverse breakdown voltage is also lower than the breakdown voltage of gate oxide layers used within the peripheral circuitry.

Diode fabrication for ESD/EOS protection

One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

Simultaneous formation of charge storage and bitline to wordline isolation

One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.

Planar structure for non-volatile memory devices

A multiplexed transistor characterization and modeling structure for testing a plurality of transistors, The characterization and modeling structure comprises a common substrate pad, a common source pad, a plurality of drain pads, and a plurality of gate pads. The characterization and modeling structure further comprises a plurality of individual transistors. Each individual transistor comprises a substrate connected to the common substrate pad, a source connected to the common source pad, a drain connected to a single drain pad, and a gate connected to a single gate pad, wherein each individual transistor is connected to a different drain pad and gate pad combination.

Device modeling and characterization structure with multiplexed pads

One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

Method of simultaneous formation of bitline isolation and periphery oxide

Disclosed herein is a method for forming an interconnect line having low conductor line capacitance between devices formed on an integrated circuit. The method comprises the steps of depositing a removable planarizing layer over fabricated device on the integrated circuit, depositing a first oxide layer over the planarizing layer, etching pillar shafts through the planarizing layer and the first oxide layer for the formation of pillars, depositing a second oxide layer over the first oxide layer filling the pillar shafts to form the pillars, etching contact shafts through the planarizing layer, the first oxide layer, and the second oxide layer to expose contacts for a first device and a second device formed on the integrated circuit, forming an electrical coupling between the contacts of the first device and the second device, etching through the planarizing layer, the first oxide layer, and the second oxide layer to provide accesses to the planarizing layer, removing the planarizing layer to form cavities separated by the pillars and the contact shafts, sealing the accesses to the cavities with a third oxide layer, and introducing an inert ambiance while sealing the accesses to the cavities whereby the dielectric constant of the cavities surrounding the interconnect line is approximately that of the inert ambiance.

Method of forming low capacitance interconnect structures on

An ESD protection device for CMOS integrated circuit inputs is disclosed. Two clamp components, coupled by a current limiting device, couple the pad to the circuitry of the chip. The device prevents damage to the circuit from an ESD of approximately 8000 or more volts at an input terminal.

Electro-static discharge protection device for CMOS integrated circuit

Growing community of inventors

Sunnyvale, CA, United States of America

David Michael Rogers