Globalfoundries Inc.

David Michael Permana

Guillaume Bouche

Jason Eugene Stephens

Andy C Wei

Roderick Alan Augur

Xiang Hu

Ravi Prakash Srivastava

Linus Jang

Tuhin Guha Neogi

Mark Alexander Zaleski

Akshey Sehgal

Craig Child

Vikrant Kumar Chauhan

Haifeng Sheng

Sudharshanan Raghunathan

Shyam Pal

Andy Chi-Hung Wei

Anbu Selvam K M Mahalingam

Dimitri R Kioussis

Jagannathan Vasudevan

At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one Mmetal structure void is formed. At least one CB structure void adjacent the Mmetal structure void is formed. An etch process is performed the Mand CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M, CB, and CA structure voids are metallized.

Method, apparatus and system for a high density middle of line flow

Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias

A method includes forming first and second contact openings in a first dielectric layer. At least the first contact opening is at least partially lined with a liner layer. A first conductive feature is formed in the first contact opening and a second conductive feature is formed in the second contact opening. A portion of the liner layer adjacent a top surface of the first dielectric layer is removed to define a recess. A barrier layer is formed above the first dielectric layer and in the recess. The barrier layer has a first dielectric constant greater than a second dielectric constant of the first dielectric layer. A second dielectric layer is formed above the barrier layer. A third conductive feature is formed embedded in the second dielectric layer and contacting the second conductive feature.

Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices

A method of fabricating a semiconductor device is provided. The method begins by providing a semiconductor device structure having electronic devices formed on a semiconductor substrate, and having an upper metal layer associated with electrical contacts for the electronic devices. The method continues by forming a diffusion barrier layer overlying the upper metal layer. Next, the method deposits a first layer of graded ultra-low-k (ULK) material overlying the diffusion barrier layer, a layer of ULK material overlying the first layer of graded ULK material, and a second layer of graded ULK material overlying the layer of ULK material. The method continues by depositing a layer of low temperature oxide material overlying the second layer of graded ULK material, and forming a layer of metal hard mask material overlying the layer of low temperature oxide material.

Method of fabricating a conductive interconnect arrangement for a semiconductor device

Growing community of inventors

Ballston Spa, NY, United States of America

David Michael Permana