Motorola Corporation

General Dynamics C4 Systems, Inc.

David Michael Harrison

Ronald V Chandos

Kerry Lucille Johns-Vano

Gerald V Piosenka

Phillip Anthony Carswell

Dadario McCutcheon

Bruce Alan Fette

William Robert Worger

Jeffery Scott Chuprun

James Edward Greenwood, Jr

Peter J Leahy

Glenn Eric Rinkenberger

Chuckwudi Perry

William K Oh

Ty Bao Lien

William Louis Perea

Alison Ii

Gregory Allen King

Christoph Andreas Roden

Margaret Reed Ennis

Kevin Thomas Campbell

A multiple access and data channel scheme is presented for reducing network communication collisions and susceptibility to jamming signals in a distributed network to increase network connectivity and communication throughput. An order wire channel (,) is used to gain access to a data channel (,). To gain access to the data channel (,), a source radio sends a transmit probe (TXP) over the order wire channel (,) to the target radio. The target radio senses its environment and responds with a receive probe (RXP) which comprises data channel transmission parameters including the data channel frequency, transmit power, spread code, and transit timing to be used for the data transmission. Source radio moves to the data channel using the data channel transmission parameters specified by the receive probe (RXP) to communicate with the target radio. If a collision occurs of the order wire channel (,), the source radio retransmits the transmit probe after a random time period.

Distributed packet communication network

A secure communication hub (,) relays local communications between low probability of intercept (LPI) user radio equipment (,) and provides a secure interface with a command center (,) through a non-geostationary commercial satellite communication system. The secure communication hub (,) includes different radio interface units (,) for communicating different data formats with the (LPI) user radio equipment (,). Encryption and decryption circuitry (,) provides for different security levels and different keys for the (LPI) user radio equipment. Links with the satellite system are secured using encryption.

Secure communication hub and method of secure data communication

A programmable crypto processing system (10) includes several processing resources (14, 16, 26) implemented on a single ULSI die. The processing system is both key and algorithm agile allowing for simultaneous execution of a variety of cryptographic programs through the use of background staging of the next program and context (key and state) during execution of a current program. The programmable crypto processing system includes a programmable crypto processor (17) for processing data units in accordance with a channel program, a crypto controller (11) for identifying a channel program, two interface processors (13, 15) for asynchronously receiving and transferring data units from and from an external host. Data units identify a particular channel program, and are processed in a selected processing engine in accordance the identified channel program. The interface processors are capable of full duplex operation and provide full physical data interface isolation for processing plain-text and cipher-text data.

Programmable cryptographic processing system and method

A programmable cryptographic system (100) provides high performance cryptographic processing support for cryptographic algorithms. Two or more independent cryptographic algorithms may be performed at the same time through the processes of background staging and algorithm multi-tasking. A four stage software instruction pipeline and dynamically programmable function units support high performance cryptographic processing performance on the order of 60 mega bits per second (Mbps) aggregate throughput.

Cryptographic processing system with programmable function units and

A cryptographic controller (100) installs and manages a channel for processing data units. The cryptographic controller (100) performs background staging of programs, context, and data units for the programmable crypto engine (14) and configurable crypto engine (16). The cryptographic controller (100) is a secure, hardware operating system capable of managing high performance crypto processing on the order of 1500 million instructions per second (MIPS).

Method and system for managing data unit processing

A processing system includes a control flow monitor (CFM) checker for verifying a sequence of instructions performed by a pipelined processor (101). The CFM checker provides fail safe assurance against run-time errors in the sequence of instructions performed by a processor. The CFM checker verifies instruction sequence during run-time within 32 instruction cycles. The processing system provides an improved system and method having a CFM checker which minimizes wasted instruction cycles when performing branch instructions in a software program. Using a prefetch capability of an instruction pipeline and storing fixwords sequentially in memory, eliminates unnecessary instructions to fetch fixword values from external tables, thereby saving instructions and instruction cycles.

System for monitoring program flow utilizing fixwords stored

A configurable cryptographic processing engine (100) provides high performance cryptographic processing support for symmetric combiner type cryptographic algorithms. As many as two independent cryptographic algorithms may be performed at the same time through the processes of background staging and algorithm multi-tasking. A 3-stage instruction pipeline, dynamically configurable cryptographic co-processor (550), and 32-bit RISC based architecture support high performance cryptographic processing performance on the order of 60 Mbps aggregate throughput.

Configurable cryptographic processing engine and method

Interface processor (IP)(50) sends and receives data units to and from an external host and a processor. The IP is capable of simultaneous, full duplex operation via high speed serial and parallel interfaces. The IP provides a highly flexible and configurable interface which is capable of interfacing to a variety of systems with minimal external hardware. The IP also provides a method of converting received data into data packets. The IP provides buffering of multiple data packets for use in systems having 'bursty' data traffic. The IP has a memory expansion capability allowing for changeable buffer capacities.

Method and processing interface for transferring data between host

A cellular communication network (10) and method operates at frequencies above 2 GHz and achieves widespread coverage within a cell (14) by adapting routing channels, symbol rates, and FEC coding processes (78) to current RF broadcast conditions. A portion of subscriber nodes (16) act as repeaters for a base node (12). If subscriber nodes (16) cannot directly communicate with the base node (12), their communications may be indirectly routed to the base node (12) through one or more repeating subscriber nodes (16'). If current conditions do not support a high data rate, then lower data rates are supported by selection of FEC coding processes (78). If increasingly inclusive FEC coding does not achieve a data rate supportable by current conditions, slower symbol rates may be used. Communications at slower symbol rates may utilize narrower frequency bands thus keeping wider frequency bands available for higher speed usage.

High bandwidth communication network and method

A tamperproof arrangement for an integrated circuit device. The arrangement includes a package and lid fabricated of heavy metals to prevent X-radiation or infrared detection of circuit operation. Sensors and control circuitry are located on the integrated circuit die itself which detect increased temperature and radiation and clear or zeroize any sensitive information included within the integrated circuit device. Electrode finger grids above and below the integrated circuit die detect physical attempts to penetrate the integrated circuit die. Critical circuit functions are segregated from non-critical functions. Power applied to the integrated circuit device is monitored and separated for critical and non-critical circuit functions.

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Mesa, AZ, United States of America

David Michael Harrison