International Business Machines Corporation

David Michael Friend

James David Strom

Grant Paul Kesselring

Joel T Ficke

Nghia Van Phan

Alan P Wagstaff

Jianguo Yao

Andrew Douglas Davies

Christopher W Steffen

Michael Sperling

Kennedy K Cheruiyot

Daniel Mark Dreps

David Arnold Luick

Todd Alan Christensen

Anthony Gus Aipperspach

Daniel Lawrence Stasiak

Peter Thomas Freiburger

Eric John Lukes

Michael James Rohn

Bradley Craig White

Erik S Unterborn

Byron D Scott

Using a burn-in operational amplifier (opamp) for a phased locked loop (PLL) regulator including activating a voltage stress mode for an integrated circuit comprising a PLL regulator for a PLL, wherein the PLL regulator comprises thin-oxide transistors, and wherein activating the voltage stress mode for the integrated circuit comprises applying an elevated voltage to an input of the PLL regulator; and enabling, during the voltage stress mode, a burn-in opamp coupled to the input of the PLL regulator, wherein enabling the burn-in opamp bias the input of the PLL regulator to a voltage lower than the elevated voltage.

Using a burn-in operational amplifier for a phased locked loop regulator

A method and circuit for implementing a level shifter for translating logic signals to output voltage analog levels, and a design structure on which the subject circuit resides are provided. The circuit includes a level shifter resistor divider string of a plurality of series connected resistors, the level shifter resistor divider string is connected between an analog voltage rail and an analog ground. A plurality of level shifter cascaded inverters are connected between respective resistors of the level shifter resistor divider string and an analog voltage rail and an analog ground. An output of the level shifter is programmed by the level shifter resistor divider string connected to the cascaded inverters.

Implementing cascade level shifter for analog voltage

A phase-frequency detector (PFD) is electrically coupled to a charge pump of a phase-locked-loop (PLL). The PFD includes a first differential latch electrically coupled to the charge pump. The first differential latch drives a differential pair of increment signals to the charge pump in response to differential pairs of both reference clock signals and reset signals. The PFD also includes a second differential latch electrically coupled to the charge pump. The second differential latch drives a differential pair of decrement signals to the charge pump in response to differential pairs of both feedback clock signals and reset signals. The PFD also includes a differential AND gate electrically coupled to both the first differential latch and the second differential latch. The differential AND gate drives the differential pair of reset signals to both of the differential latches in response to the differential pairs of both increment signals and decrement signals.

Differential phase-frequency detector

A system includes a voltage controlled oscillator (VCO) having an adjustable amplitude. The amplitude of the VCO may be adjusted by adjusting voltage level present at a center tap node of an inductor. The VCO may have an adjustable amplitude that may be programmed on a chip-by-chip basis based on a chip parameter, power consumption, or oscillator performance.

VCO selection and amplitude management using center tap inductor

The present disclosure discloses an IC with an electromigration (EM) monitor. The IC includes a functional circuit configured according to a first value of a parameter related to EM tolerance. The IC also includes a dummy version of the functional circuit configured according to a second value of the parameter. The second value causes the dummy version of the functional circuit to be more sensitive to an EM event than the functional circuit. Upon the EM monitor determines that the EM event occurs in the dummy version of the functional circuit, the EM monitor asserts a signal indicating that the EM event has occurred in the dummy version of the functional circuit and providing a warning that the EM event is likely to occur in the functional circuit.

Electromigration monitor

Embodiments herein describe a transmission line used to carry an AC signal (e.g., a high-speed clock signal) between two different voltage domains in an IC. Instead of dividing the transmission line into multiple segments each with a buffer, in one embodiment the transmission line is arranged to form a capacitor. That is, the conductive material forming the transmission line is arranged in the IC to result in a desired capacitance. This capacitance can be used to replace a discrete capacitor that would otherwise be used with a buffer (e.g., level shifter) located at the end of the transmission line for converting the AC signal from a first voltage domain to a second voltage domain.

Wire capacitor for transmitting AC signals

A phase-locked loop (PLL) circuit, sense amplifier circuit, and method of operating a sense amplifier circuit are disclosed. The sense amplifier circuit comprises first and second operational amplifiers, each operational amplifier respectively comprising a non-inverting input terminal, an inverting input terminal, and an output stage comprising a current gating circuit having two current gating input terminals, the output stage coupled with an output terminal, the output terminal providing a feedback signal to the inverting input terminal. The input voltage signal is received across the non-inverting input terminals of the first and second operational amplifiers, and is received across the two current gating input terminals of each of the first and second operational amplifiers, wherein the sense amplifier circuit generates a sense voltage signal across the output terminals of the first and second operational amplifiers.

Low power amplifier

Phase locked loop with sense amplifier circuitry

A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

Voltage controlled oscillator runaway prevention

A phased locked loop (PLL) incorporates multiple voltage controlled oscillators including one that operates in a lower frequency range than an operational VCO used by the PLL. A VCO selection circuit allows the system to select from one or more alternate VCOs. A ring oscillator VCO may be used as the alternate VCO for a PLL that uses a LC VCO for the operational VCO. While the ring oscillator VCO provides lower performance, the ring oscillator VCO allows the system with the PLL to be run at a lower speed for testing, debugging or characterization.

Phased locked loop with multiple voltage controlled oscillators

A circuit for implementing a control voltage mirror is provided. A filter includes a filter capacitor connected to a control voltage and a distal side of the capacitor connected to a voltage reference. The control voltage mirror includes an operational amplifier having a positive input connected to the control voltage, and a negative input is connected to an output and coupled to the distal side of the capacitor. Voltage across the capacitor is held to be near or at zero volts, substantially eliminating capacitor leakage current.

Control voltage mirror circuit

A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

Growing community of inventors

Rochester, MN, United States of America

David Michael Friend