Texas Instruments Corporation

David Michael Alter

Charles W Brokish

Jamil Chaoui

A system and method of dynamic offset compensation that is particularly adaptable to analog-to-digital conversion performed in control applications employing highly integrated Digital Signal Processor (DSP) devices. The system providing dynamic compensation of Analog-to-Digital Converter (ADC) zero level offset errors includes an integrated DSP device with a multi-bit ADC and a PWM waveform generator for producing at least one PWM output, and an external low pass filter. The ADC receives an analog input signal and converts it into a corresponding digital output signal. The DSP device measures the zero level offset of the ADC output signal, and dynamically controls characteristics of the PWM output based on the measured offset. The low pass filter receives the PWM output and applies a corresponding controlled DC output voltage to the low reference voltage input of the ADC to dynamically compensate for the zero level offset error.

Dynamic compensation of analog-to-digital converter (ADC) offset errors using filtered PWM

A delayed adaptive least-mean-square (LMS) filter, which has one filter coefficient per tap and acquires a new data sample each frame, calculates a finite impulse response (FIR) filter output and updates the filter coefficients using an error term based on the FIR filter output calculated during the preceding frame. The calculations for each tap are performed in a single clock cycle. The filter can be implemented using a general purpose, programmable digital signal processor (DSP) architecture having two multiply and accumulate circuits (MACs), with or without an arithmetic logic unit (ALU), and preferably implements its memory buffers as dual-access or dual-port RAM or banked memory.

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Burlington, MA, United States of America

David Michael Alter