Mindspeed Technologies, Inc.

Western Digital Technologies, Inc.

Iii Holdings 1, LLC

Sandisk Technologies Inc.

Rambus Inc.

Viasat, Inc.

David Meyer

Prashant Jain

Greg Graham

Bradford C Lincoln

Anand Narayan

Shay Benisty

Stephen Gold

Amir Segev

Anand P Narayan

James J Walsh

Satish Babu Vasudeva

Vivek Shivhare

Aakash Sahai

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a parent physical function (PF), receive one or more child PFs, determine whether any part of a first child command of a first child PF of the one or more child PFs can be executed prior to receiving approval from the parent PF, and start executing the first child command. The controller is further configured to initialize an indirect queue, set fetching pointers of the indirect queue to the first child command, mimic a doorbell for the first child command, fetch the first child command, determine whether the first child command has started execution by a child PF flow, and complete the first child command.

Latency on indirect admin commands

A storage system caches logical-to-physical address table entries read in volatile memory. The logical-to-physical address table entries are stored in codewords. The storage system can vary a number or size of an entry in a codeword. Additionally or alternatively, each codeword can store both complete and partial logical-to-physical address table entries. In one example, a codeword having 62 bytes of data and two bytes of error correction code stores 15 complete logical-to-physical address table entries and one partial logical-to-physical address table entry, where the remainder of the partial entry is stored in another codeword. This configuration strikes a good balance between storage space efficiency and random-access write performance.

Storage system and method for storing logical-to-physical address table entries in a codeword in volatile memory

In one embodiment, a memory system stores data encrypted with a cipher key in a block of a page in non-volatile memory, reads the cipher key version number associated with the page, determines whether the cipher key version number associated with the page is different from a cipher key version number of the cipher key used to encrypt the data and, if it is, writes a data pattern encrypted with the cipher key into the other blocks of the page, and stores the cipher key version number of the cipher key used to encrypt the data in the storage space in the non-volatile memory. Other embodiments are provided.

Memory system and method for writing data to a block of an erased page

An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data. Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

Methods for managing alignment and latency in interference suppression

Disclosed is a method of controlling a receiver. A group identifier or modulation and coding scheme is sent in a physical layer header. This group identifier or modulation and coding scheme, or both, determine whether the corresponding physical layer frame should be fully demodulated and decoded. If it is not necessary to fully demodulate and decode the physical layer frame, the receiver may disable its demodulator, decoder, or both. This results in a power savings. A hub device sends the group identifier or modulation and coding scheme in the physical layer header. This allows receivers that are not addressed by the group identifier, or modulation and coding scheme, to disable at least a portion of their circuitry. Disabling at least a portion of circuitry saves power consumption and dissipation. The hub device may also send control messages to tell the receiver which group identifiers, or modulation and coding schemes, they should respond to.

Reducing receiver power dissipation

Methods for managing alignment and latency in interference cancellation

Ring access control circuitry comprises a receive interface, a host interface coupled to the receive interface, a mate interface coupled to the host interface, a flow control agent coupled to the mate interface, a transmit interface coupled to the flow control agent, and a wrap path coupled from between the flow control agent and the transmit interface to between the receive interface and the host interface. A wrap is initiated over the wrap path in response to a link failure. The ring being controlled could be a resilient packet ring.

Flow control for communication ring access control

Wrap path for communication ring access control

A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues. The SAR determines if either status queue is full by comparing the address written by the SAR into such status queue with the address written by the host periodically to the SAR where the host is in the status queue. The host determines if either control queue is full by comparing the address written by the host into such control queue with the address written by the SAR periodically to the host where the SAR is in the control queue.

Asynchronous transfer mode system for, and method of, writing a cell payload between a control queue on one side of a system bus and a status queue on the other side of the system bus

Data (e.g. legacy LAN traffic) segmented into packets provide a header and a cell payload for each cell in each packet. The cell payloads are transferred to a region address in a host memory in accordance with determinations by a control memory. When the cell payload is to be transmitted from the host memory, the cell payload for a particular region address is combined with the header stored in the control memory for such address. Streaming data (e.g. voice or video) occurs at a regular rate and is not necessarily broken into packets. The streaming data is segmented to provide cell headers and cell payloads. The cell payloads are then transferred to a host receive FIFO in accordance with a determination by the control memory and are stored in a data sink. Cell payloads from a data source are transferred into a host transmit FIFO at a particular rate and are transferred from the host transmit FIFO preferably at a substantially constant rate higher than the particular rate. These FIFO cell payloads are combined with the headers in the control memory. When the cell payloads in the host transmit FIFO become almost depleted, the transmission of the cell payloads from the host transmit FIFO is skipped to allow the host transmit FIFO to receive additional cell payloads from the data source. The transmit and receive FIFO's respectively maintain cell alignment by providing particular controls with respect to the minimum and maximum number of cell payloads in the FIFO's.

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Lakewood, CO, United States of America

David Meyer