International Business Machines Corporation

Seiko Epson Corporation

David Meltzer

Mayan Moudgill

Erdem Hokenek

Gregory A Blum

Muralikumar A Padaparambil

Joel Abraham Silberman

Clair John Glossner, Iii

Tat C Wu

Sang Hoo Dhong

Harm Peter Hofstee

Michael John Hargrove

Edward J Nowak

Kerry Bernstein

Wayne Frederick Ellis

Stephen Victor Kosonocky

Kevin John Nowka

Norman Jay Rohrer

Howard L Kalter

Victor V Zyuban

Thomas James Heller, Jr

Thomas R Puzak

Erik Richter Altman

Leon L Wu

Jeffrey H Dreibelbis

Rudolph N Rechtschaffen

Frederick J Aichelmann, Jr

James H Pomerene

Richard R Konian

Michael Ignatowski

Peter Edwin Cottrell

Frank J Sparacio

Wen-Yuan Wang

Samuel R Levine

John M Angiulli

Brian King Flacks

Arun K Ghose

Eko Lisuwandi

Rex H Blumberg

A method, algorithm, circuits, and/or systems for demodulation in an amplitude modulated (AM) radio receiver are disclosed. In one embodiment, a radio receiver can include an amplifier configured to receive a radio frequency (RF) input signal and a gain control signal, and provide an amplified signal, an automatic gain control (AGC) circuit configured to receive a high threshold comparator output and provide the gain control signal, a mixer configured to combine the amplified signal and a local oscillation signal and provide a mixed output, a high threshold comparator configured to compare the mixed output with a reference level and provide the high threshold comparator output, and a low threshold comparator configured to compare the mixed output with the reference level and provide an output of the radio receiver.

Dual threshold demodulation in an amplitude modulation radio receiver

A method, algorithm, circuits, and/or systems for amplitude shift keying (ASK) modulation are disclosed. In one embodiment, a sampling demodulator includes a comparator configured to compare an ASK modulated input to a predetermined voltage level and provide a comparison result, a pulse stretcher with a sampler configured to sample the comparison result a plurality of times for each of a plurality of cycles of the ASK modulated input to generate a bit stream and digital logic configured to determine a value for each data bit in the ASK modulated input from the bit stream, and a digital filter configured to filter an output of the digital logic, thereby providing a demodulated signal.

Sampling demodulator for amplitude shift keying (ASK) radio receiver

Apparatuses and methods for receiving an amplitude modulated signal in one of two modes depending on the quality of the received signal. In a first mode, the amplitude modulated signal is converted directly to a baseband signal. In a second mode, the amplitude modulated signal is converted to an intermediate frequency signal. The present invention advantageously combines direct conversion and image-rejection heterodyne receiver topologies with a relatively large degree of component reuse and relatively few additional components.

Dual demodulation mode AM radio

A receiver for receiving an amplitude modulated (AM) signal may include a first and a second detector for detecting the maximum and minimum envelope values, respectively, of the received AM signal and an equalizer for periodically equalizing the maximum and minimum envelope values. A method for receiving an AM signal may include unidirectionally increasing a first output signal up to the maximum envelope value, unidirectionally decreasing a second output signal down to the minimum envelope value, and periodically equalizing the first and the second output signals.

Envelope detector for AM radio

Apparatuses, circuits, and methods for receiving at least one radio signal in a radio controlled timing apparatus using a single timing source. The present invention advantageously eliminates the need to provide an additional timing source to receive at least one radio signal, and therefore reduces the material cost and eliminates many engineering challenges.

Radio watch

Circuits and methods for recovering a periodic signal from a data signal. One circuit generally includes (1) a recovery circuit configured to produce a reference signal from the data signal, (2) a frequency detector circuit configured to produce a detector output in response to the reference signal and a recovered periodic signal, (3) a decision circuit configured to produce a decision output in response to the detector output and the recovered periodic signal (or a periodic derivative of that signal), and (4) a charge pump configured to produce a pump output, where the level of the pump output corresponds to a value of the decision output. The circuits and methods generally include those that embody one or more of the inventive concepts disclosed herein. The present invention advantageously provides smooth signal acquisition without use of an external clock.

Circuits and methods for acquiring a frequency of a data bitstream

A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includes a vector data file comprising a plurality of storage elements for storing data elements of the data vectors. A pointer array is coupled by a bus to the vector data file. The pointer array includes a plurality of entries wherein each entry identifies at least one storage element in the vector data file. The at least one storage element stores at least one data element of the data vectors, wherein for at least one particular entry in the pointer array, the at least one storage element identified by the particular entry has an arbitrary starting address in the vector data file.

Vector register file with arbitrary vector addressing

Circuits and methods for compensating a variable oscillator for process and/or operational variations. The circuit generally comprises (a) a replica oscillator, (b) a counter configured to count pulses of the replica oscillator and to produce a count signal, and (c) a compensation circuit configured to provide an adjustment signal to the variable oscillator in accordance with the count signal. The method generally comprises the steps of (a) counting the number of pulses of a replica oscillator signal, and (b) providing an adjustment signal to the variable oscillator in accordance with the number of pulses counted. The present invention advantageously provides a largely digital method to compensate a variable oscillator for process, voltage, and temperature variations.

Methods and apparatus for compensating a variable oscillator for process, voltage, and temperature variations using a replica oscillator

A system and method is provided for processing a first instruction set and a second instruction set in a single processor. The method includes storing a plurality of instructions of the second instruction set in a plurality of buffers proximate to a plurality of execution units, executing an instruction of the first instruction set in response to a first counter, and executing at least one instruction of the second instruction set in response to at least a second counter, wherein the second counter is invoked by a branch instruction of the first instruction set.

System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form

A method, algorithm, software, architecture, circuit, and/or system for detecting an idle condition and maintaining a frequency of a clock/data recovery circuit are disclosed. In one embodiment, a method of maintaining a frequency of a clock/data recovery circuit can include the steps of: (i) comparing a difference value from a differential signal with a predetermined threshold (or value); (ii) controlling a variable frequency oscillator (VFO) with a frequency detector when the difference value is less than the threshold for at least a predetermined integration time; and (iii) controlling the VFO with a phase detector receiving the differential signal when the difference value is greater than the threshold. Embodiments of the present invention can advantageously provide a reliable and simplified design approach for clock data recovery (CDR) circuits operable with low power mode transmitters.

Method and apparatus for maintaining a clock/data recovery circuit frequency during transmitter low power mode

A frequency synthesizer, for integration in a low voltage digital CMOS process, controls a VCO using a dual loop structure including an analog loop and a digital loop. The digital loop includes an all digital frequency detector, which controls a center frequency of the VCO. The analog loop includes an analog phase detector and charge pump, which add phase coherence to the frequency controlled loop. The analog loop reduces the noise of the digital logic and VCO, and the digital control provides frequency holdover and very low bandwidth. The bandwidth of the digital loop is made smaller than the bandwidth of analog loop, and is preferably 200 times smaller. This parametric difference allows two separate control inputs to the VCO, one from the analog loop and one from the digital loop, with both inputs functioning relatively independently of each other.

Frequency/phase locked loop clock synthesizer using an all digital frequency detector and an analog phase detector

A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.

Digital signal processor with cascaded SIMD organization

Circuits and methods and for generating oscillator outputs using standard integrated circuit components. The basic circuit generally includes two inverters and a variable capacitor to configure a delay of the circuit input and/or output. The oscillator circuit generally includes a plurality of inverter circuits, at least one of which uses a variable capacitor to adjust a delay between stages, and thereby adjust a frequency of oscillation. Thus, the oscillator outputs may be tuned using a single control voltage. The method generally includes the steps of (1) applying an operating voltage to a ring oscillator comprising a plurality of stages; and (2) applying a control voltage to a variable capacitor coupled to a node between at least two of those stages. The circuits have particular advantage in quadrature oscillators, and may be easily implemented using widely available CMOS technology.

Circuits for voltage-controlled ring oscillators and method of generating a periodic signal

An improved integrated LC resonator and methods for making and using the same are disclosed. The resonator includes (i) a first capacitor plate; (ii) an inductor over and in electrical communication with the first capacitor plate; and (iii) a second capacitor plate over and in electrical communication with the inductor. The method of making includes sequentially forming a first capacitor plate, a first dielectric layer thereon, a first via and an inductor, a second dielectric layer on the inductor, and a second via and a second capacitor plate. Each of the capacitor plates and the inductor are generally formed in different integrated circuit layers (for example, different metallization layers). Embodiments of the present invention can advantageously provide an integrated LC resonator tank having: (i) relatively high Q by reducing or minimizing parasitic effects; and (ii) relatively high shielding from the semiconductor substrate.

Integrated resonator structure and methods for its manufacture and use

A method, algorithm, software, architecture, circuit, and/or system for assisting pull-in of a phase-locked loop (PLL) are disclosed. In one embodiment, a PLL can include: (i) a phase detector that may receive a serial data stream and output a pump control signal; (ii) a charge pump that can receive the pump control signal and substantially determine a frequency control when a precharge signal is de-asserted; (iii) a precharge/filter circuit that may connect to the charge pump and may substantially determine the frequency control when the precharge signal is asserted; and (iv) an oscillator that may connect to the precharge/filter circuit and may provide a recovered clock in response to the frequency control, where the recovered clock may be correlated to a frequency of the serial data stream. The frequency control may be current and/or voltage based, for example. Embodiments of the present invention can advantageously provide a reliable and simplified design approach for pulling-in a PLL lock.

Growing community of inventors

Wappingers Falls, NY, United States of America

David Meltzer