Linear Technology Corporation

Analog Devices International Unlimited Company

David McLean Dwelley

Jeffrey Lynn Heath

Robert Loren Reay

Andrew J Gardner

Trevor Wayne Barcelo

Heath Stewart

Kirk Su

Ryan Huff

Michael Paul

John Arthur Stineman, Jr

Robert C Dobkin

Jonathan Noah Simon

Mark Alan Lemkin

Lance Robert Doherty

Thor Juneau

David B Bell

Alain Pierre Levesque

Brett Warneke

Gordon Alexander Charles

Jacob Herbold

Harry Joseph Kleeburg

David Stover

Kok Yong Sim

Erik Soule

A battery system monitor includes cell measurement circuits (CMCs) that each measure a voltage at or current through a pair of terminals of a respective associated battery module from among a plurality of plurality of battery modules in a battery system. Wireless communication transceivers (WCTs), each associated with a different CMC, transmit voltage or current measurement information of the associated CMC across a wireless communication link. A controller receives the voltage or current measurement information from the wireless communication transceivers for monitoring the state of operation of the battery system. Battery system monitoring is improved through synchronization of clocks in different CMCs or WCTs to enable synchronous sampling of multiple battery modules, through systems for determining relative positions of battery modules in a series coupling of battery modules between terminals of the battery system, and through improvements to the reliability of wireless communication.

Wireless sensing for battery systems

One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first port and second port to power the second node via the first port of the second node. All nodes in the network are then sequentially powered up in this manner. If there is a fault between the first node and the second node, the second node will be powered by another node connected to the second port of the second node.

Fault-tolerant power network

In one embodiment, a master device has a first port and a second port and initially applies a DC voltage only to the first port. A plurality of slave devices, each have a third port and a fourth port, are serially connected to the master device in a ring, via conductors, starting at the first port and ending at the second port. The conductors simultaneously carry the DC voltage and differential data. Each slave device, after performing a detection routine, then sequentially applies the DC voltage to the adjacent downstream slave device in a first direction around the ring. If the master does not detect the presence of the DC voltage at its second port, the master device applies the DC voltage to both the first port and the second port to sequentially power up the slave devices in both directions around the ring of slave devices.

Power over data lines system with redundant power connections

In a method performed by a PoE system, a PSE provides data and operating voltage over Ethernet wires to a PD. Before the full PoE voltage is supplied, the PSE generates a low current signal received by the PD. A circuit in the PD, connected across its input terminals, has a characteristic analog response to the PSE signal corresponding to the PD's PoE requirements, such as whether the PD is a Type 1 or Type 2 PD. The circuit may be a certain value capacitor, zener diode, resistor, or other circuit. The PSE may generate a fixed current, fixed voltage, or time varying signal. Upon the PSE sensing the magnitude of the analog signal response at a particular time, the PSE associates the response with the PoE requirements of the PD. The PSE then applies the full PoE voltage in accordance with the PD's PoE requirements.

Detection and classification scheme for power over Ethernet system

A PoDL system includes a PSE connected via a wire pair to a PD, where differential data and DC power are transmitted over the same wire pair. Typically, low voltage/current detection and classification routines are required upon every powering up of the system to allow the PD to convey its PoDL requirements to the PSE. Various techniques are described that simplify or obviate such start-up routines or enable increased flexibility for the PoDL system. Such techniques include: ways to specify a particular PD operating voltage; ways to disable the PD's UVLO circuit during such routines; using opposite polarity voltages for the two routines; using voltage limiters or surge protectors to convey the PoDL information; detecting loop resistance; using a PSE memory to store previous results of the routines; and powering the PD communication circuit using the wire pair while the PD load is powered by an alternate power source.

Power over data lines system providing a variable voltage to powered device

Power over data lines system using voltage clamp in PD for detection or classification

In one embodiment, a PoDL system includes a PSE that uses high side and low side circuit breakers that uncouple the PSE voltage source from the wire pair in the event that a fault is detected. Faults may include a temporary short to ground, or to a battery voltage, or between the wires. The breakers perform an automatic retry operation in the event the fault has been removed. The voltages on the wires in the wire pair may be monitored to determine whether the voltages are within a normal range or indicative of a fault condition. Other embodiments are disclosed.

Circuit architectures for protecting against PoDL wire faults

Detection and classification scheme for power over ethernet system

Power over data lines detection and classification scheme

A system includes a master and a slave coupled via a wire pair for transmitting differential data. The master and slave are each powered by a local DC power supply. In a normal mode, a DC voltage and differential data are supplied over the same wire pair. The differential data is processed by a PHY AC-coupled to the wire pair. To enter a low power sleep mode, such as due to a temporary non-use of the system, the master interrupts the DC voltage on the wire pair, which signals to the slave to enter the sleep mode. The system is woken up by reapplying the DC voltage to the wire pair to signal to the slave to wake up. Only the DC path, and not the data path, is used for signaling the sleep mode and awake mode, so the data path can be disabled to conserve power.

System with sleep and wake up control over DC path

A PoDL system includes a PSE supplying DC power and Ethernet data over a single twisted wire pair to a PD. Prior to coupling the DC voltage source to the wire pair, the PD needs to receive sufficient power to perform a detection and classification routine with the PSE to determine whether the PD is PoDL-compatible. The PSE has a low current, pull-up current source coupled to a first wire in the wire pair via a first inductor. This pull-up current charges a capacitor in the PD to a desired operating voltage, and the operating voltage is used to power a PD logic circuit. The PD logic circuit and a PSE logic circuit then control pull-down transistors to communicate detection and classification data via the first wire. After the handshaking phase, the PSE then applies the DC voltage source across the wire pair to power the PD for normal operation.

1-wire bus PD detection and classification scheme for ethernet PoDL

A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and differential Ethernet data over a single twisted wire pair to a Powered Device (PD). Due to start-up perturbations, PD load current variations, and other causes, dV/dt noise is introduced in the power signal. Such noise may be misinterpreted as data unless mitigated somehow. Rather than increasing the values of the passive filtering components conventionally used for decoupling/coupling the power and data from/to the wire pair, active circuitry is provided in the PSE, PD, or both to limit dV/dt in the power signal. Such circuitry may be implemented on the same chip as the PSE controller or PD controller. Therefore, the sizes of the passive components in the decoupling/coupling networks may be reduced.

PoDL system with active dV/dt and dI/dt control

Novel techniques for balancing power or current drawn from multiple power supply inputs by controlling switching circuits associated with the respective power supply inputs. Each switching circuit may be controlled so as to limit current in its transformer or inductor in each switching cycle to a peak or average current value common to all switching circuits.

Controlling switching circuits to balance power or current drawn from multiple power supply inputs

A PSE includes a PSE controller that performs a handshaking routine with any PDs connected to the data wire pairs and spare wire pairs and applies power to the data wire pairs and spare wire pairs, via a switch, if certain conditions are met. Two different levels of currents are supplied to different terminals of the PSE controller that are connected to the data wire pairs and the spare wire pairs, and the resulting voltages are measured. The voltages are used to determine the PD impedances at the ends of the data wire pairs and spare wire pairs to determine whether a PD is connected to the data wire pair, whether another PD is connected to the spare wire pair, or whether a single PD is connected to both the data wire pairs and the spare wire pairs.

PSE controller in PoE system detects different PDs on data pairs and spare pairs

Technique for providing power to a powered device (PD) over a cable having first and second sets of twisted pairs, such as signal pairs and spare pairs. Power Sourcing Equipment (PSE) circuitry is coupled via a first switch to the second set, e.g. to the spare pairs. A switch control circuit turns the first switch off to enable the PSE circuitry to perform a prescribed operation in connection with the PD over only the first set, e.g. over the signal pairs, and turns the first switch on to enable the PSE circuitry to perform the prescribed operation in connection with the PD over the first and second sets.

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Santa Barbara, CA, United States of America

David McLean Dwelley