Micron Technology Incorporated

Lsi Logic Corporation

Lsi Corporation

David Matthew Springberg

Graeme M Weston-Lewis

Matthew David Rowley

Jackson L Ellis

David R Noeldner

John Edward Maroney

Lyle E Adams

Jefferson E Singleton

Dustin James Carter

Paul A Suhler

Peter Edward Kaineg

Jeffrey Paul Grundvig

Stephen D Hanna

Richard Martin Born

Jason S Goldberg

Boris Livshitz

Various embodiments enable a memory sub-system to perform a read operation based on consolidated memory region description data, which can be generated based on a memory region description data (e.g., SGL) provided by a host system for the read operation.

Operation based on consolidated memory region description data

A processing device receives a request to write data to a memory device. The processing device generates a codeword based on the data. The codeword comprises the data and error correction code. The processing device generates a compressed codeword by compressing the codeword. The processing device stores the compressed codeword on a page of the memory device.

Compression-based data operations in a memory device

Disclosed is a power management integrated circuit with embedded address resolution protocol functionality. In one embodiment, a device is disclosed comprising a data storage device; and an address resolution protocol (ARP) state machine communicatively coupled to the data storage device and included within a power management integrated circuit (PMIC), the ARP state machine configured to assign an address to the data storage device and validate requests for data stored in the data storage device received over a bus.

Power management integrated circuit with embedded address resolution protocol circuitry

An indication of a capacity of a CMB elasticity buffer and an indication of a throughput of one or more memory components associated with the CMB elasticity buffer can be received. An amount of time for data at the CMB elasticity buffer to be transmitted to one or more memory components can be determined based on the capacity of the CMB elasticity buffer and the throughput of the one or more memory components. Write data can be transmitted from a host system to the CMB elasticity buffer based on the determined amount of time for data at the CMB elasticity buffer to be transmitted to the one or more memory components.

Providing information for a controller memory buffer elasticity status of a memory sub-system to a host system

A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.

Managing host communication with a regulator in a low power mode

A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and a controller configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The storage disk is partitioned into at least first and second regions, with the first region having a substantially higher average data transfer rate than the second region and being utilized to store data that is accessed more frequently than data stored in the second region. In one embodiment, the data stored in the first region is not stored in the second region or in any other region of the storage disk, and is randomly distributed across a plurality of sectors of the first region. The first region may comprise one or more outer annular zones of the storage disk and the second region may comprise one or more inner annular zones of the storage disk.

Disk-based storage device with frequently accessed partition

A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry comprises an inter-track interference detector configured to process a signal read from at least a given track of the storage disk via the read/write head in order to detect interference in that signal from at least one other track of the storage disk. The control circuitry further comprises an inter-track interference based head position controller configured to adjust the positioning of the read/write head responsive to the detected interference.

Disk-based storage device with head position control responsive to detected inter-track interference

A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry comprises a disk controller and read channel circuitry, with the read channel circuitry comprising a read channel memory. The control circuitry is further configured to selectively permit the disk controller to access the read channel memory. For example, the disk controller may be permitted to access the read channel memory only when the read channel circuitry is not performing a read operation.

Disk-based storage device having read channel memory that is selectively accessible to disk controller

A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry is further configured to adjust at least one parameter of a write signal for a target bit to be written to the storage disk based on respective magnetization polarities of one or more adjacent bits previously written to the storage disk.

Growing community of inventors

Fort Collins, CO, United States of America

David Matthew Springberg