Texas Instruments Corporation

David Matthew Curran

Bhaskar Srinivasan

Guruvayurappan Mathur

Poornika Fernandes

Scott William Jessen

Shih Chang Chang

Russell Duane Fields

Thomas Terrance Lynch

Abbas Ali

Dhishan Kande

Stephen Arlon Meisner

Ye Shao

Daniel J Curran

Stephen Arion Meisner

Neil L Gardner

Eric Robert Trumbauer

Jon Evan Button

Charles David Gordon

Brant William Paquette

Vince Christian Samek

Michael Jay Jenson

In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

Integrated circuits having dielectric layers including an anti-reflective coating

A method of providing a semiconductor device and a computer-readable medium having instructions for performing the method are disclosed. The method includes receiving a first wafer defect map that defines comparison regions and identifies visual defect locations for a wafer. A format of the comparison regions is determined, with the format chosen from a group including die-to-die, partial-shot-to-partial-shot and full-shot-to-full-shot. If the comparison format is not die-to-die, mapping information is received that provides die locations within the comparison regions. A wafer layout map is provided that identifies die locations within the wafer.

System and method for electronic die inking after automatic visual defect inspection

An integrated circuit (IC) includes a substrate with a semiconductor surface layer including functional circuitry having a plurality of interconnected transistors including a dielectric layer thereon with a metal stack including a plurality of metal levels over the dielectric layer. A thin film resistor (TFR) layer including at least one metal is within the metal stack. At least one capacitor is within the metal stack including a capacitor dielectric layer over a metal bottom plate formed from one of the metal levels. The capacitor top plate is formed from the TFR layer on the capacitor dielectric layer and there is at least one resistor lateral to the capacitor formed from the same TFR layer.

Thin film resistor and top plate of capacitor sharing a layer

An integrated circuit (IC) includes a semiconductor surface layer on a substrate including functional circuitry having circuit elements configured together with a metal-to-polysilicon capacitor on the semiconductor surface layer for realizing at least one circuit function. The metal-to-polysilicon capacitor includes a bottom plate including polysilicon, a capacitor dielectric including at least one capacitor dielectric layer on the bottom plate, a top plate on the capacitor dielectric, and contacts through a pre-metal dielectric layer that contact the top plate and contact the bottom plate. In lateral regions relative to the capacitor the capacitor dielectric layer has a thickness in a range between about 5% and about 50% of a thickness of the capacitor dielectric of the metal-to-polysilicon capacitor.

IC with top side capacitor having lateral regions with thinned capacitor dielectric

Shutter with solar cell lamellae

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Plano, TX, United States of America

David Matthew Curran