Stmicroelectronics (research & Development) Limited

Stmicroelectronics Gmbh

Ge Oil & Gas UK Limited

Vetco Gray Controls Limited

Stmicroelectronics R&d Limited

Baker Hughes Energy Technology UK Limited

David Martin Smith

Andrew Marsh

Robert G Warren

Davide Sarta

A hydraulic flushing system includes a hydraulic downhole control line that runs from a hydraulic source to a surface controlled sub-surface safety valve of an underwater hydrocarbon extraction facility, where the hydraulic downhole control line includes a directional control valve. The hydraulic flushing system further includes a purge line coupled to the hydraulic downhole control line downstream of the directional control valve to a service line. The purge line includes a fluid isolation valve therein to enable purging of a hydraulic fluid. The hydraulic flushing system further includes a service line coupled to the purge line via the fluid isolation valve to store the purged hydraulic fluid.

Hydraulic flushing system

A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.

Processor communications

An arrangement of at least two arithmetic logic units carries out an operation defined by a decoded instruction including at least one operand and more than one operation code. The operation codes and at least one operand are received and corresponding executions are performed by the arithmetic logic units on a single clock cycle. The result of the execution from one arithmetic logic unit is used as an operand by a further arithmetic logic unit. The decoding of the instruction is performed in an immediately preceding single clock cycle.

Apparatus for switching a plurality of ALUs between tree and cascade configurations

A request routing circuit includes m inputs for receiving m input request signals and n outputs for outputting a set of n output request signals. A routing subsystem within the request routing circuit is provided between the m inputs and the n outputs and comprises k inputs and n outputs, where m is greater than k, and where the routing subsystem is configured to operate over a plurality (m/k, rounded up to the next integer) of cycles to provide the set of n output request signals based on the m inputs to the n outputs.

Arrangement, method, integrated circuit and device for routing requests

A system and a method detects errors when writing data to a memory in a computer system. An error detection memory write request for writing an error detection value to a memory location within the memory section is issued, the error detection value being associated with the block of data. A data memory write request for writing the block of data to the memory section is issued such that at least part of the block of data is written to the memory location. A check is performed to determine whether the error detection value in the error detection memory write request corresponds to the block of data in the data memory write request.

Error detection

A method of verifying the integrity of code in a programmable memory, the method including: receiving the code from an insecure memory; generating error detection bits for the code as it is received from the insecure memory; storing the code and the error detection bits in the programmable memory; and verifying the integrity of the code stored in the programmable memory by performing an authentication check on the code and the error detection bits stored in the programmable memory.

Loading secure code into a memory

A method and system of controlling access to a programmable memory including: allowing code to be written to the programmable memory in a first access mode; preventing execution of the code stored in the programmable memory in the first access mode; verifying the integrity of the code stored in the programmable memory; if the integrity of the code stored in the programmable memory is verified, setting a second access mode, wherein in the second access mode, further code is prevented from being written to the programmable memory, and execution of the code stored in the programmable memory is allowed.

An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.

Reset in a system-on-chip circuit

A method is disclosed for operating a computer system in order to validate data stored in a plurality of data files in a database. Each of the data files have an associated file type and are arranged in a plurality of data stores in the database. At least one of the data files is a data dependent file which contains data dependent upon data in one or more other files of the data store. The method includes the steps of selecting a file locator which is associated with a respective one data store in the database, via the selected file locator identifying a first dependent file and identifying one or more other files on which said first file is dependent. For each identified file a first file reader is selected which is associated with the file type of the identified file. Via each selected first file reader a predetermined parameter of the identified file is determined. The method further includes the steps of comparing the predetermined parameter from the first file with that from the or each other file and responsive to the comparison step providing an output signal for each data file indicating whether the data file is valid.

Design flow checker

A system for use in controlling and/or testing an underwater hydrocarbon production system, has a number of control modules for controlling well trees. The control modules are provided, not at the trees, but at a control center for location underwater. The trees are in communication with associated ones of the control modules.

Controlling and/or testing a hydrocarbon production system

Integrated circuitry including a clock circuit powered by a first power supply and a secondary circuit powered by a second power supply. The secondary circuit includes a control signal output for supplying a control signal to the clock circuit and a clock data output for outputting new clock data to the clock circuit. The clock circuit includes: clock generator means for generating current clock data and outputting it to the secondary circuit; detector means for monitoring voltage from the second power supply and generating a system reset signal for supply to the secondary circuit in the event the voltage falls below a predetermined level; a first latch having a reset operable by a predetermined state of the system reset output generated by the detector means; a comparator accepting as inputs the control signal from the secondary circuit and an output of the first latch; and a multiplexor accepting as data inputs the clock data from the secondary circuit and the clock data from the clock circuit, and accepting as a control input the output of the comparator. The integrated circuitry is configured such that when the secondary circuit is not asserted and the control signal is asserted, the current clock data in the clock circuit is replaced with the new clock data. Moreover, when the first latch is reset, the comparator and multiplexor prevent current clock data from being replaced by data from the secondary circuit.

Growing community of inventors

Bristol, United Kingdom

David Martin Smith