Hewlett-packard Development Company, L.P.

David Marshall

Karl Joseph Bois

David W Quint

Elias Gedamu

Larry Jay Thayer

Denise Man

Philip L Barnes

John E Tillema

Michael H Cogdill

Ian Erickson

Karl Joseph B Is

A data bus for a printed circuit board is disclosed having a plurality of lines separated by a substrate. A method is also disclosed for creating a bus with a reduced reflection of signal energy at the interface between the bus and a receiving agent connected to the bus. The lines in the bus include data lines and at least two strobe lines that are positioned adjacent each other to take advantage of the known impedance inherent to their dominant coupling. The bus includes separate data-line terminations and strobe-line terminations connected to the data lines and strobe lines, respectively. The separate terminations have values matched to impedances calculated from the separate sets of lines to more effectively reduce the reflected energy by more accurately matching the impedances on the lines.

Data bus with separate matched line impedances and method of matching line impedances

A method of enhancing noise margin on digital signal lines of a system includes steps of evaluating impedances and lengths of the digital signal lines. Resonances of each digital signal line are determined, and target waveforms for each digital signal line optimized for noise margin are determined. A configuration is generated for a programmable device driver to configure the device driver to generate the waveform optimized for noise margin. An alternative embodiment selects waveforms, and corresponding configurations, from a group of possible waveforms at boot time to ensure that data is transferred with optimum noise margins. Also claimed is apparatus embodying bus drivers capable of driving a bus with a waveform approximating blended trapezoidal and sinusoidal edge shapes, this waveform being optimum for noise margin in certain systems having multidrop busses.

Method and apparatus for high speed bus having adjustable, symmetrical, edge-rate controlled, waveforms

Two reference voltages and two differential receivers are used to detect low-to-high and high-to-low transitions on an input signal and set a received signal output. One reference voltage is set near but under the electrical high voltage level and the other is set near but above the electrical low voltage level. The reference voltage that is closest to the input signal is designated as the active reference voltage. When the input signal crosses the active reference voltage digital value of the received signal output is changed. When the input signal then crosses the inactive reference voltage, the inactive reference voltage is made the active reference voltage. A dead-time is then waited where input signal crossings of the active reference voltage are ignored. After the dead-time, input signal crossings of the active reference voltage will change the received signal output.

Dual switching reference voltages

A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.

Dynamic control of switching reference voltage

Buffer that includes an input node, an output node, and a three-transistor charge pump circuit is coupled to the input node and the output node. The buffer generates an output signal that is a delayed version of a signal presented at the input node. The three-transistor charge pump includes a first transistor (e.g., a pass transistor) that includes a drain electrode that is coupled to the input node, a gate electrode and a source electrode; a second transistor that includes a drain electrode that is coupled to a first predetermined voltage, a gate electrode coupled to the drain electrode of the second transistor, and a source electrode coupled to the gate electrode of the first transistor; and a capacitive element that includes a first electrode that is coupled to the source electrode of the second transistor and the gate electrode of the first transistor and a second electrode that is coupled to the output node.

Charge pump circuit, passive buffer that employs the charge pump circuit, and pass gate that employs the charge pump circuit

A six-drop bus has each driver or receiver terminated at the characteristic impedance of Z . Each driver or receiver is connected to a segment of transmission line with a characteristic impedance of Z . Three of these segments are connected at a first point. The other three of these segments are connected at a second point. The first and second points are connected by a central transmission line with a characteristic impedance of Z /

Six-drop bus with matched response

An embodiment of the invention provides a circuit and method for reducing power in dynamic circuits. A large single pre-charge FET is used to pre-charge the pre-charge nodes of all dynamic logic blocks contained in a plurality of dynamic logic blocks. The large single pre-charge FET replaces all smaller individual FETs that normally would be used. Because smaller FETs typically have more subthreshhold leakage than larger FETs, the overall subthreshhold leakage is reduced. The large pre-charge FET only replaces smaller pre-charge FETs that have the same pre-charge signal going to their gates.

Growing community of inventors

Fort Collins, CO, United States of America

David Marshall