Xilinx, Inc.

David Mark

Randy J Simmons

Yuezhen Fan

Zhi-min Ling

Joe W Zhao

Min Luo

Xiao-Yu Li

Eric Thorne

Felino E Pagaduan

Yongjun Zheng

Yung-Cheng Chen

Huy-Quang Le

Kazi S Afzal

A method of evaluating an inline inspection recipe compares the capture rate of metal pattern defects in bounding boxes arising from failed electrical test vectors to the capture rate after the bounding box is shifted. A difference between the first and second capture rates indicates whether the inline inspection recipe is valid for capturing killer defects, or if the inline inspection recipe needs to be adjusted. In a particular example, the electrical test vectors are directed at a selected patterned metal layer of an FPGA (M), and the metal pattern defect data for the selected patterned metal layer is mapped to the bounding box determined by the electrical test vector.

Method of metal pattern inspection verification

A method of monitoring the functionality of a wafer probe is disclosed. The method comprises applying a multi-site probe to a plurality of semiconductor dies; comparing the failure rate of a first probe site of the multi-site probe with the failure rate of a second probe site of the multi-site probe for a test of the plurality of semiconductor dies; and determining that a probe site of the multi-site probe is defective based upon comparing the failure rate of the first probe site of the multi-site probe with the failure rate of the second probe site of the multi-site probe. A system for monitoring the functionality of a wafer probe site is disclosed.

Method of and system for monitoring the functionality of a wafer probe site

According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to a second node and a test signal driver coupled to the first node of the conductor. The test signal driver receives a test signal using a first clock signal, while a plurality of detector circuits coupled to the conductor between the first node and the second node to detect an output at the plurality of nodes using a second clock signal. According to other embodiments, circuits for determining the location of a defect in a programmable logic device are disclosed. Finally, various methods for determining the location of a defect in an integrated circuit are described.

Circuit for and method of determining the location of a defect in an integrated circuit

A method and test configuration for performing a gross I/O functionality test at wafer sort is described. The method uses a current injector, such as a pullup or a pulldown on an I/O pad, to inject current at the I/O pad, and based on the resulting voltage, determines if the I/O characteristics of the IC meet the performance criteria set by a manufacturer. In some embodiments, the test configuration can comprise an output buffer, which can be a tristate buffer, and/or an input buffer for verifying the performance of those components. The method and test configuration allow such tests to be performed at wafer sort without a precision measurement unit and without direct access to the I/O pad to be tested.

Method for gross I/O functional test at wafer sort

The embodiments of the present invention enable a new metal diagnosis pattern based on a production test pattern to quickly identify open and short circuits of metal lines which cannot be probed, such as the long lines of a programmable logic device, and to further isolates the fault location for physical failure analysis. According to one aspect of the invention, a circuit locally drives a plurality of metal long line segments to determine whether a defect in a line is a short circuit, or further to identify the location of an open circuit.

Test circuit for and method of identifying a defect in an integrated circuit

Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.

Method and circuits for localizing defective interconnect resources in programmable logic devices

Methods and systems for testing PLD interconnect lines, e.g., interconnect lines driven by a plurality of programmable buffers. Each programmable buffer has an associated memory element. The memory elements are configured to form a shift register, with one of the buffers and the interconnect line inserted between two of the memory elements. The signal path through the shift register is tested using a first test pattern. Partial reconfiguration is then used to change the insertion point of the interconnect line in the signal path by changing the configuration of the interconnect structure and using a second one of the buffers. A second test pattern is then used to test the second buffer. This sequence is repeated until each of the buffers has been tested. Because only small changes are required, the partial reconfiguration requires loading only small amounts of configuration data, significantly reducing test time compared to presently-known test methods.

Methods of testing interconnect lines in programmable logic devices using partial reconfiguration

Method and apparatus for localizing faults within an integrated circuit is described. For example, a programmable logic device (PLD) is configured with a test pattern. A test stimulus is applied to the test pattern. State data responsive to the test pattern is obtained. The state data may be obtained from a readback datastream generated by the PLD. The expected state data may be generated by a second PLD that is known to contain no faults. The state data is compared with expected state data to produce difference information. The difference information is used, or more particularly is iteratively generated, to localize a fault or faults within a unit under test.

Method and apparatus for localizing faults within a programmable logic device

A method and test configuration for performing a gross input leakage test at wafer sort is described. The method uses a pullup and pulldown on an I/O pad to inject current at the I/O pad, and, based on the resulting voltage, determines if the leakage current is excessive. The method allows an input leakage test to be performed at wafer sort without a precision measurement unit and without direct access to the I/O pad to be tested.

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San Jose, CA, United States of America

David Mark