Arm Limited

David Madsen

Richard F Bryant

Kim Richard Schuttenberg

Sriram Samynathan

Lalit Bansal

Apparatus comprises source circuitry to provide data items; buffer circuitry having a set of buffer entries to hold one or more data items, provided by the source circuitry, for delivery to one or more destinations within a respective delivery latency, in which a buffer entry holding an initial data item becomes available to hold another data item in response to delivery of the initial data item to its respective destination; and control circuitry to control acceptance of data items from the source circuitry for holding by the buffer circuitry, the control circuitry being configured to control the buffer circuitry to accept a given data item when: (i) a buffer entry is available to hold the given data item and (ii) the delivery latency of data items including the given data item held by the buffer circuitry is such that at least a threshold number of buffer entries may be made available within no more than a threshold availability period.

Apparatus and method for handling delivery of data from a source to one or more destinations

An apparatus and method are provided for handling access requests. The apparatus has processing circuitry for processing a plurality of program threads to perform data processing operations on data, where the operations identify the data using virtual addresses, and the virtual addresses are mapped to physical addresses within a memory system. The cache storage has a plurality of cache entries to store data, an aliasing condition existing when multiple virtual addresses map to the same physical address, and allocation of data into the cache storage being constrained to prevent multiple cache entries of the cache storage simultaneously storing data for the same physical address. Cache access circuitry is then responsive to an access request specifying a virtual address, to utilise a cache index at least partially determined from the specified virtual address to identify at least one cache entry within the cache storage, and to detect whether a hit is present within the at least one cache entry by comparing a physical address portion associated with that cache entry with a tag portion of the physical address corresponding to the specified virtual address. Remap handling circuitry is then arranged whilst a first program thread is in the process of performing an exclusive operation using a first virtual address to identify a specified physical address whose data is stored in the cache storage, to detect a remap condition when a second program thread issues a second program thread access request of at least one type that specifies a second virtual address that exhibits the aliasing condition with the first virtual address. In the presence of the remap condition, the remap handling circuitry remaps the cache index at least partially determined from the second virtual address, so that the remapped cache index as then used by the cache access circuitry matches the cache index at least partially determined from the first virtual address. This provides an effective mechanism for avoiding potential live-lock scenarios that can otherwise arise.

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Chandler, AZ, United States of America

David Madsen