Intel Corporation

International Business Machines Corporation

David M Wu

Talal K Jaber

Chih-Jen M Lin

Nandor G Thoma

James W Davis

Anil K Sabbavarapu

Robert M Swanson

Vivek K De

Ming Lei Zhang

Yibin Ye

Anthony Correale, Jr

Ali Keshavarzi

Larry Edward Thatcher

Srinivas Patil

Hehching Harry Li

Humberto Felipe Casal

Praveen K Parvathala

Michael Thomas Dibrino

Kim E O'Donnell

Richard M Doney

Jacquelin Babakanian

Mark S Garvin

Grant W McFarland

Zhuoyu Bao

Madhukar K Reddy

Erwin A Tate

Andrew Kegl

Paven R Sunkerneni

Imin P Chen

Naga Gollakota

A scan architecture and design methodology yielding significant reduction in scan area and power overhead is generally presented. In this regard, an apparatus is introduced comprising a plurality of combinatorial logic clouds, scan cells coupled with the combinatorial logic clouds, the scan cells to load test vectors, wherein the scan cells comprise a plurality of first type scan cells and second type scan cells sequentially coupled with separate combinatorial logic cloud outputs, and a first scan clock and a second scan clock, wherein the first scan clock controls the first type scan cells and the second scan clock controls the second type scan cells. Other embodiments are also described and claimed.

Scan architecture and design methodology yielding significant reduction in scan area and power overhead

In one embodiment, the present invention includes a processor having a plurality of logical units to perform operations on data. Each unit may include a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from input signals to the unit. In turn, each MISR may includes bit cells, each having a first cell to receive incoming data and controlled by a first clock signal, a second cell to receive an output of the first cell and controlled by a second clock signal, a mask cell to receive an output of the second cell and to generate a mask signal responsive to a mask clock signal, and a multiplexer coupled between the first and second cells. Other embodiments are described and claimed.

Common test logic for multiple operation modes

A technique for testing a memory array. More particularly, embodiments of the invention relate to a memory array testing architecture in which a memory array within a device under test (DUT) is able to be tested at speeds substantially similar to those under typical operating conditions of the memory array without incurring significant die real estate and power penalties.

Method and apparatus for testing a memory array

A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.

Flexible scan architecture

According to some embodiments, a circuit includes a Domino state element, a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal, and a slave latch to receive a second clock signal and to output the value in response to the second clock signal. Some embodiments provide a first state element coupled to a first node, a master latch coupled to the first state element, the master latch to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, a second state element coupled to a second node, the second node sequential to the first node, and a slave latch coupled to the second state element, the slave latch to receive a second storage signal, a second load signal, a second clock signal and a second scan value signal.

Scan cell systems and methods

An apparatus and method of testing an integrated circuit by downloading a sequence of randomly weighted bits into a scan chain in which each bit has a distinctly determined weight generated in real-time by a weight generator. The weight generator has a switch controlled by a stored bit particular for each bit of the randomly weighted bits that determines the weight of the bit. The control signal is stored in a memory that is downloaded into the switch in synchronization with the generation of the bit. Preferably, the memory is on-die, and furthermore is a part of the integrated circuit.

Weighted random pattern test using pre-stored weights

A method and device are provided for stress testing a chip. The chip may be partitioned into at least a first block and a second block. Burn-in stress testing may be performed on electronic devices within the first block without simultaneously performing burn-in stress testing on electronic devices within the second block. A burn-in stress testing device may perform the burn-in testing. A control device may be coupled to the burn-in stress testing device to enable burn-in stress testing on electronic devices within at least the first block of the chip without simultaneously enabling burn-in stress testing on the second block of the chip.

Method and apparatus for providing rotational burn-in stress testing

A method and apparatus for using weighted random patterns in a partial scan test. A computer generates deterministic patterns on the partial scan design. Deterministic patterns that have the same number of capture clocks between adjacent scan loads are grouped together into pattern groups. A computer then determines a set of weights corresponding to each of the pattern groups. A tester then uses these weights as a filter to weighted random test patterns and applies these filtered weighted random test patterns along with the appropriate number of capture clock pulses to a device under test.

Method for application of weighted random patterns to partial scan

A method and system for modeling the behavior of a circuit are disclosed. A list specifying a plurality of transistors within the circuit and interconnections between the plurality of transistors is provided. Each fan node within the circuit is identified, where a fan node is defined as a point of interconnection between two or more of the plurality of transistors from which multiple nonredundant current paths to power, ground, or an input of the circuit exist. A fan node equation set is constructed that expresses a logical state of each fan node of the circuit in response to various transistor gate signal states. In addition, an output node equation is constructed that expresses a logical state of an output node of the circuit in terms of selected fan node logical states and specified transistor gate signal states. In response to receipt of a set of states of inputs to the circuit, a logical state of the output node is determined utilizing the fan node equation set and the output equation in order to model behavior of the circuit.

Method and system for modeling the behavior of a circuit

The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop ('PLL') circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period. In both cases, if the number of cycles counted is not what was expected, then it is known that the sense clock signal was not properly produced by the PLL circuit.

System and method for testing a clock signal

Groups of DCVS (Differential Cascode Voltage Switch) circuits are interconnected by single-track data transfer connections. Each group contains one or more DCVS tree circuits, through which data signals propagate only on dual-track connections. In each group, at least one DCVS tree circuit is configured as an input boundary tree, and at least one tree circuit is configured as an output boundary tree. All data inputs externally applied to a group, are transferred only through input boundary trees of the group, and all data outputs transferred out of a group leave the group only through output boundary trees of the group. If a group has only a single tree, that tree serves as input and output boundary tree of the group. Each input boundary tree of each group has one or more associated primary shift register latch (SRL) circuits through which all external data inputs to that tree are transferred. Such external data inputs are received through the single-track connections mentioned above. The primary SRL circuits are also used to present predeterminable test data inputs to respective trees, and to collect primary test data outputs representing signals received through the single-track connections. In such usage, the SRL circuits are connected as a scannable shift register. Each output boundary tree has an exclusive-OR (XOR) circuit for indicating if the respective tree is in a legal or illegal state. The XOR circuits connect to secondary scannable SRL circuits for external presentation of illegal state indication. The primary test data outputs together with the externally presented illegal state indications form a basis for detecting and locating any faulty state in any group.

Fully testable DCVS circuits with single-track global wiring

Disclosed is a basic DCVS (differential cascode voltage switch) tree construct, which can be used as a uniform basis for constructing DCVS logic circuits, register-latch circuits and circuits which can be conditioned individually to function as either or both DCVS logic and register-latches. In addition to logic and load sections that may be identical to corresponding sections of prior art DCVS trees, this construct contains gating elements for providing unique functions of isolation, precharge support and latch input coupling. The isolation function is used to electrically isolate the logic and load sections from each other, so that each section can be made to operate in a mode which is independent of the other section. The precharge support function allows precharging of circuits in the logic section without involvement of the load section. The latch input coupling function allows signals to be applied to and latched in the load section from a source other than the respective logic section. Use of arrays of such trees for constructing complex logic circuits is described.

Basic DCVS circuits with dual function load circuits

The present invention implements self testable boundary logic by using a tristate pass gate and a tristate receiver in combination with a linear feedback shift register, a storage register, and level sensitive scan design (LSSD) techniques. The linear feedback shift register (LFSR) shifts data into a storage register which is connected to the data inputs of the boundary logic through the tristate pass gate. The outputs of the tristate input receiver are also connected to the inputs of the boundary logic so that the boundary logic can receive data from both the data input of the integrated circuit (data path) or from the storage register connected to the LFSR. The tristate pass gate and receiver are enabled through a self test signal such that when the pass gate is enabled the receiver is not enabled and vice versa. In this way the boundary logic can only get data from either the storage register or through the receiver but not both. In this configuration data from the storage register can be input into the boundary logic without going through a multiplexer in the data path and incurring the associated delay. The boundary logic can then be self tested using ordinary LSSD techniques. This self testing can also be performed with a minimum of additional silicon area being used for the self test structures.

Growing community of inventors

Austin, TX, United States of America

David M Wu