Tilera Corporation

Massachusetts Institute of Technology

Mellanox Technologies, Ltd.

Princeton University

David M Wentzlaff

Anant Agarwal

Matthew Mattina

Carl Ramey

Patrick Robert Griffin

Walter Lee

Mark B Rosenbluth

Ian Rudolf Bratt

Christopher J Jackson

Bruce Edwards

Richard Schooler

Christopher D Metcalf

Liewei Bao

Chyi-Chang Miao

Kenneth M Steele

Shane Bell

John A Amann

Mathew Hostetter

Richard Conlin

Georgios Tziantzioulis

Ben Harrison

Kevin Joyce

Christine Deignan

Fei Gao

A processor includes a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is associated with information indicating whether data stored in the cache memory is shared among multiple processor cores.

Cache coherency in multiprocessor system

According to various embodiments, an in-memory computation system is disclosed. The system includes a dynamic random access memory (DRAM) module. The system further includes a memory controller configured to violate a timing specification for the DRAM module and activate multiple rows of the DRAM module in rapid succession to enable bit-line charge sharing.

System and method for in-memory compute

The flow of data in an integrated circuit is controlled. The integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a receive buffer to store data from the switch. At a first tile, a count is maintained of data that has been sent to a second tile without receiving an acknowledgement up to a credit limit. At the second tile, data that arrives from the first tile when the receive buffer is full is sent to a memory outside of the tile.

Flow control in a parallel processing environment

An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.

Architecture emulation in a parallel processing environment

Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.

Programming in a multiprocessor environment

An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.

Managing cache memory in a parallel processing environment

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Computing in parallel processing environments

Transferring and storing data in multicore and multiprocessor architectures

Virtual architectures in a parallel processing environment

Growing community of inventors

Cambridge, MA, United States of America

David M Wentzlaff