Lsi Logic Corporation

Symbios, Inc.

Lsi Corporation

David M Weber

Timothy E Hoglund

John Matthew Adams

Stephen M Johnson

Mark A Reber

Michael B Anderson

Kenneth C Schmitt

Systems and methods for allocating assets to a plurality of devices are presented. In one embodiment, devices may be communicatively connected to one another through a device loop. Each device may be configured for determining a portion of an asset that it will use. A controller may also be communicatively connected to the communication medium and configured for determining a capacity of the asset. The controller may transfer control information to the devices so as to allocate the asset to the devices based on the capacity of that asset. In another embodiment, each of the devices may be communicatively connected directly to the controller rather than to one another.

Systems and methods for allocating an asset to interconnected devices

A mechanism if provided for testing newly-manufactured integrated circuits at the wafer stage. Built-in self-test circuitry is used to test each of the die on a wafer in parallel. Then, when a defect is detected, the die marks itself (e.g., by physically destroying a portion of itself through burnout). The present mechanism eliminates the inefficiencies of serial testing of die and of mechanical latency as each die is positioned for testing.

Method and apparatus for automatic marking of integrated circuits in wafer scale testing

A method and apparatus for transmitting data in a node having a buffer. A first set of data is received in a buffer for transmission to a target node. The first set of data is sent to the target node. Responsive to an indication that the target node is unable to receive data, a second set of data is loaded into the buffer for transmission to another target node, while the first set of data is retained in the buffer.

Method and apparatus for transmitting Data

A method and apparatus in a source node for transmitting data to a target node. Responsive to a request to transmit data to the target node, a determination is made as to whether a selected period of time has passed without data transmitted from the source node being received by the target node. Responsive to detecting the selected period of time has passed without data transmitted from the source node being received by the target node, a determination is made as to whether space is available in the target node to receive the data. Responsive to a determination that space is unavailable in the target node, generating an indication that the target node is blocked is generated.

Method and apparatus for transmitting data to a node in a distributed data processing system

A method of fabricating a semiconductor wafer includes the step of fabricating a number of die on the wafer. The method also includes the step of fabricating a memory device on the wafer. The method further includes the step of testing the number of die with a die testing apparatus so as to obtain test data associated with the number of die. In addition, the method includes the step of storing the test data obtained during the testing step in the memory device. Moreover, the method includes the step of retrieving the test data from the memory device. Yet further, the method includes the step of operating a packaging apparatus so as to package a first die of the number of die based on the test data. A semiconductor wafer is also disclosed.

Method and apparatus for maintaining test data during fabrication of a semiconductor wafer

A dual-phase clock divider circuit provides the ability to generate high speed complementary clocks with low skew. The dual-phase clock divider circuit runs off a single clock input, such as provided by a high speed VCO. This eliminates the effect of clock skew in the highest speed portion of the circuit. The dual-phase clock divider then generates complementary outputs of low skew to be used by other clocked elements.

High speed single phase to dual phase clock divider

A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on ship processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order. Additionally, the context managers also determine when all frames within a sequence have been received. A link control unit is provided in which loop management is provided when the host is connected to a loop. Management of the loop includes implementing mechanisms to initiate acquisition of the loop and initiate a release of the loop in response to conditions in which data is received and transmitted by the host and by other nodes on the loop.

Single chip protocol engine and data formatter apparatus for off chip host memory to local memory transfer and conversion

A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on chip processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order. Additionally, the context managers also determine when all frames within a sequence have been received. A link control unit is provided in which loop management is provided when the host is connected to a loop. Management of the loop includes implementing mechanisms to initiate acquisition of the loop and initiate a release of the loop in response to conditions in which data is received and transmitted by the host and by other nodes on the loop.

Method and apparatus for managing access to a loop in a data processing

A method and apparatus of a synchronizer circuit for transferring signals between two clock domains in which a first synchronizer unit and a second synchronizer unit form a hand-shaking protocol. In particular, an input event from a source clock domain is captured in an input unit and a first signal is asserted indicating that the input signal is to be transferred to a target clock domain. This first signal is synchronized to the clock signal in the target clock domain at the first synchronizer unit, causing assertion of a second signal. The second signal is coupled to an output unit which generates an output event signal for a single clock period.

Method and apparatus for synchronously transferring signals between

A method and associated apparatus for using a content addressable memory (CAM) to process timed events in a process control application. A time value field in each CAM entry identifies the time at which a corresponding event is to be processed. An event identifier field in each CAM entry identifies the event to be processed. A time value generator applies signals indicative of a time value to the CAM. The CAM returns as data on its output signal paths any entries whose time value fields correspond to the applied time value signals. The event identifier field applied to the output signal paths of the CAM is then applied to the process controller to identify an event to be processed. The methods and apparatus of the present invention are applicable, for example, in communication controller devices wherein a protocol requires timed event processing for standardized communications (e.g., Fibre Channel or FDDI). In addition, the apparatus and methods may be applied to computer controlled processes to relieve the CPU of the overhead processing burden of processing interrupts corresponding to 'timer ticks' unrelated to any event. In addition, application of the present invention to computer process control applications (including operating system processing of timed events) relieves the CPU of the processing overhead associated with creating, searching, and maintaining list or queue data structures for the scheduled events.

Method and apparatus for using a content addressable memory for time

A method and associated apparatus for using a primary FIFO and one or more secondary FIFOs in parallel to simplify flow control and routing in packet communication operations wherein at least one FIFO (buffer) is associated with each of a plurality of receiving nodes or components within a receiving node. The present invention applies received packets simultaneously to a primary FIFO and to all associated secondary FIFOs in the receiver of a packet communications link. After receipt of a packet, the packet is removed from any secondary FIFOs which correspond to receiver nodes or components to which the packet was not routed. For all receiving nodes or components to which the packet was routed, if the packet was stored in each associated secondary FIFO without overflow, then the packet is also purged from the primary FIFO. If any secondary FIFO overflowed by storage of the received packet, then the packet is purged from the overflowed FIFO and the packet remains stored in the primary FIFO for further processing. Flow control signals are generated and applied to the transmitting source as required in accordance with the status of the primary FIFO. The secondary FIFOs are not directly relevant to flow control logic. The receiving component corresponding to each secondary FIFO locates the next packet for processing by inspecting the associated secondary FIFO as well as the primary FIFO if the secondary FIFO overflowed. These methods and apparatus simplify flow control and routing control in packetized communication receivers.

Method and apparatus for using multiple FIFOs to improve flow control

A method and associated apparatus for automating the filtration and generation of information in a packetized communication system. A filtration table includes entries used in recognizing a valid packet received at a node in a communication system. A mask field in each entry is applied to appropriate fields in the packet (e.g. the ordered set as applied to Fibre Channel communication systems) to determine the validity of the packet with regard to the receiving node. Rules in a field of each entry further qualify the recognition of a received packet (e.g. ordered set) by testing the reception of the packet against other logical rules. Action fields in each record permit definition of actions to be invoked automatically (e.g. automatic adjustment of fill transmissions in Fibre Channel applications) in response to receipt and recognition of a particular packet. The set of packets recognized by the receiving node may be modified by adding, deleting, or modifying the entries in the filtration table. The programmable filtration thereby permits simple modifications to the protocol supported by the receiving node. Programmable generation capabilities of the present invention permit rapid integration of additional packets (e.g. ordered sets) transmitted in response to perceived packets in the receiving node. Programmable parameters in the receiving node permit automatic generation and transmission of packets in accordance with the parameter settings at the time of packet transmission.

Growing community of inventors

Monument, CO, United States of America

David M Weber