Seiko Epson Corporation

David M Tucker

Lawrence P Chee

Brett Anthony Cheng

William Low

Juraj Bystricky

Kevin Gillett

A computer system includes an operator input device, a central processing unit (CPU), and a display device, such as a liquid crystal display (LCD) or cathode ray tube (CRT) providing a visible image to the computer user as an output of computer activity. The computer system includes a video display controller (VDC) with a graphics generator. This VDC receives image information, such as text or graphics generated by the CPU, or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and responsively provides image signals driving the CRT or LCD display. The VDC includes a power saving controller implementing one of several available power saving modes dependent upon one or more of several possible inputs. Each of the power saving modes includes the same list of VDC functions which may individually be enabled or disabled in each power saving mode dependent upon a bit value entered into a register of the power saving controller. Each of the power saving modes is ranked with the others in an order of succession. Accordingly, when each mode of power saving is enabled, it disables the lower-ranked modes of power saving. In turn, each mode of power saving is disabled and succeeded if a higher-ranked mode is enabled.

Computer system with video display controller having power saving modes

A computer system includes one or more display devices, such as a cathode ray tube (CRT) or liquid crystal display (LCD) for providing a visible display to a user of the computer system. The computer system includes a video display controller (VDC) with a graphics generator. This VDC receives image information, such as text or graphics generated by a processor (CPU) or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and provides signals driving one or both of the CRT or LCD displays. The VDC includes a sequencer and controller (SEQC) for a dynamic random access memory (DRAM) which is interfaced with the VDC. The SEQC arbitrates requests from various devices of the computer system for access to the DRAM, and facilitates these access according to a multi-tiered priority scheme. Accordingly, more efficient access to the DRAM is insured for the various devices of the computer system, and utilization of the DRAM, as well as the time of devices which are sometimes required to wait for access to the DRAM is improved.

Computer system with efficient DRAM access

A clocking system including a line clock system for generating normal line clock pulses to the digital display during the period when the image is being rendered and for generating fast line clock pulses to the digital display during the vertical blanking period to address the otherwise unaddressed vertical region. The clocking system further includes a pixel clock system for generating normal pixel clock pulses to the digital display during the period when the image is being rendered and for generating fast pixel clock pulses to the digital display during the horizontal and vertical blanking periods to address the otherwise unaddressed horizontal and vertical regions.

System and method for fast clocking a digital display in a multiple

The present invention is directed to a display FIFO module for use in DRAM interface that includes a DRAM controller sequencer which prioritizes requests for DRAM access received from various modules, such as a CPU, a blit engine module, and a half frame buffer logic module, etc. The display FIFO module is connected between the DRAM controller sequencer and a display pipeline which is connected to a display device. The display FIFO module issues low and high priority requests for DRAM access to the DRAM controller sequencer for loading the FIFO with display data to be transferred to the display device. The low priority request is issued at the earliest time when the display FIFO is capable of accepting new data without overwriting unread data. This is determined by comparing the FIFO data level against a predetermined low threshold value. The low priority request is issued when the FIFO data level falls below or is equal to the low threshold value. A high priority request is issued when the FIFO mug receive new data or FIFO underrun will occur. This is determined by comparing the FIFO data level against a predetermined high threshold value. The high priority request is issued when the FIFO data level falls below or is equal to the high threshold value.

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Vancouver, Canada

David M Tucker