Linear Technology Corporation

David M Thomas

Richard James Reay

Alfio Zanchi

Joseph L Sousa

Jesper Steensgaard-Madsen

Andrew Joseph Thomas

Alfo Zanchi

A sampling circuit may include a sampling capacitance, an electronic sampling switch, and a switch controller. The electronic sampling switch may have a control input that controls whether the electronic sampling switch is in a sample state or a hold state. The electronic sampling switch may connect the sampling capacitance to an input signal while in the sample state and disconnect the sampling capacitance from the input signal while in the hold state. The switch controller may control the control input to the electronic sampling switch so as to cause the electronic sampling switch to be in the sample state during one period and the hold state during another period. While in the sample state, the switch controller may cause the impedance of the electronic sampling switch that is seen by the input signal to be substantially independent of the voltage of the input signal. The switch controller may include a pre-charge circuit that pre-charges the control input to the electronic sampling switch prior to each commencement of the sample state to approximately the average of the voltage of the input signal and the voltage on the sampling capacitance immediately prior to each commencement of the sample state. The amount of the pre-charging may be substantially independent of the voltage of the input signal.

Bootstrap sampling circuit with accurately averaging pre-charge circuit

Circuits and methods for converting a signal from analog to digital. A random number generator provides a random number to a memory. The memory is preconfigured to include codes of predetermined digital to analog (DAC) configurations that provide the maximum amount of DAC gradient suppression. At least one Flash reference generation DAC (FRGD) has an input coupled to the memory unit and an output providing a reference voltage level for its respective Flash comparator. The Flash comparators compare the analog input signal to their respective reference voltage and provide a digital output signal based on the comparison.

Systems and methods for randomizing component mismatch in an ADC

Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch.

System and methods to improve the performance of semiconductor based sampling system

A current source is switchable between two precisely defined output currents. A terminal of a coupling capacitor is coupled to the gate of an output MOSFET. The other terminal of the capacitor is switched between two reference voltages to toggle the output MOSFET to output the selected one of the two currents. A switchable bias voltage source is coupled to the gate only during the on state of the output MOSFET to set the gate voltage of the output MOSFET. The current output of the current source is quickly and accurately changed. A reference MOSFET is not directly coupled to the output MOSFET, so there are no slow settling components coupled to the gate of the output MOSFET.

Capacitively coupled switched current source

Circuits and methods that improve the performance of voltage reference driver circuits and associated analog to digital converters are provided. A voltage reference driver circuit that maintains a substantially constant output voltage when a load current is modulated by an input signal is provided. The voltage reference driver circuit synchronously decouples a voltage regulation circuit from the load circuit when modulating events such as pulses caused by the load circuit during a switching interval are generated, preventing disturbance of the regulation circuitry and keeping its output voltage substantially constant.

Circuits and methods to reduce or eliminate signal-dependent modulation of a reference bias

Systems and methods for reducing the magnitude of signal dependent capacitance are provided. Capacitance canceling circuitry is operative to generate cancellation capacitance in response to the magnitude of a signal, which may be the same signal that produces the undesired signal dependent capacitance, to at least partially cancel the signal dependent capacitance.

Circuits and methods for canceling signal dependent capacitance

Circuits and methods are provided that compensate for dynamic errors caused by voltage drops across a switch coupled in series with a capacitor in an electrical circuit such as a track-and-hold circuit. In such circuits, the capacitor should provide the same voltage as a signal coupled to the switch, but does not because of the switch voltage drop. The switch can be, for example, a MOSFET or more particularly a CMOS device. Dynamic errors are compensated for by measuring the voltage drop across the switch and then effectively adding the measured voltage drop to a voltage provided by the capacitor.

Dynamic error compensation in track-and-hold circuits

Improved pipelined successive approximation analog-to-digital converter circuits are provided. Some embodiments of the present invention comprises two stages in which a first portion of the total bits are evaluated in the first stage of the circuit and then the residue is passed to the second stage of the circuit that evaluates the remaining portion. By operating both stages simultaneously, the throughput is increased. These embodiments utilize two matched buffers to isolate the first and second stages from switching errors of a sampling circuit and the loading effects of comparators associated with the two stages. In another embodiment, upon completion of the conversion of the MSBs, the remaining input signal or residue signal is amplified by a preamp and the output is subsequently sampled by a residue sample and hold circuit (S/H). After the residue is sampled by the residue S/H, the second stage begins to solve the least significant bits (LSBs). The second stage is a matched copy of the first stage. Furthermore, if the CDACs and the preamps corresponding to the two stages are matched, the actual value of the preamp gain does not affect converter linearity. In yet another embodiment, a single preamp buffer is switched between the first and second stages. The preamp provides buffering of the top plates of the capacitor array from the residue sampling switch.

Pipelined successive approximation analog-to-digital converters

An analog-to-digital converter circuit (ADC) is described which comprises capacitor based digital-to-analog converter circuits (CDACs) coupled to the inputs of a voltage comparator wherein a reference voltage of one CDAC section has been scaled with respect to a reference voltage of another CDAC section such that one CDAC section adds additional resolution to the other CDAC section. The invention may be applied to single input ADCs as well as to differential ADCs with either type operating in either unipolar or bipolar mode. Also described are various known approaches to both single input and differential CDAC-based successive approximation ADCs, as well as a novel technique of capacitive input voltage attenuation for differential ADCs.

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Colorado Springs, CO, United States of America

David M Thomas