Marvell International Limited

Marvellworld Trade Ltd.

Apple Inc.

David M Signoff

Wayne A Loeb

Ming He

Renaldi Winoto

Li Lin

Morteza Nick

Shu-Hsien Liao

Jinho Park

Yuan Lu

Yi Zhao

Kefei Wu

Alden Chee Ho Wong

Sai-Wang Tam

Nuntha Kumar Krishnasamy Maniam

Fei Wang

Yung Chen

Xiang Guan

Song Hu

Ahmed I Hussein

Philip Godoy

Anuranjan Jha

Xinhua Chen

Preeti S Mulage

Mahdi Forghani

This disclosure is directed to reducing output voltage distortions of Variable Gain Amplifiers (VGAs). A VGA may include a number of amplifiers each providing a portion of a total gain of the VGA. For example, a processing circuit may select one or more of the amplifiers of the VGA to provide the output signal with a selected gain. However, the selected amplifiers may provide amplified signals with one or more distortion signals when receiving a bias voltage. Systems and methods are described to reduce or cancel the distortion signals of the selected amplifiers by providing a subthreshold nonzero bias voltage (e.g., a weak voltage) to the remaining (e.g., non-selected) amplifiers of the VGA. For example, the non-selected amplifiers may receive the weak voltage to provide distortion signals with similar voltage amplitude and out of phase compared to the distortion signals of the selected amplifiers.

Variable gain amplifier with subthreshold biasing

Radio frequency (RF) transmitters of a device (aggressor device) may unintentionally transmit a high-power output signal to antennas of a receiving device (victim device). In some RF systems, a victim device may have no or little protection between its antennas and transistors in an integrated circuit. Performance or lifetime of the transistors may be negatively impacted due to large voltage swings that may result from the high-power signal received from the aggressor device. To prevent or mitigate impact to performance or lifetime of the transistors due to the large voltage swings, protection circuitry including switches and a direct current (DC) power source (e.g., a charge pump) may be implemented at an input of a receiver of the victim device to shunt the power from sensitive circuit components of the victim device.

Charge pump-enabled circuit protection switch

A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal. However, while each unit cell may be generally the same, there may be variations such as non-linearity or noise in the analog output depending on which unit cells are activated for a given digital signal value. For example, as additional unit cells are activated for increased values of the analog signal, the fill order in which the unit cells are activated may affect the linearity/noise of the DAC. The decision units may be programmable to select which branches of the fractal DAC to activate, changing the fill order based on a fill-selection signal. The fill order may be set by a fill controller via the fill-selection signal to account for manufacturing variations, gradients in the supply voltage, output line routing, and/or environmental factors such as temperature.

Programmable digital-to-analog converter decoder systems and methods

An electronic device may include wireless circuitry having mixer circuitry configured to receive an oscillator signal from phase-locked loop circuitry. The phase-locked loop circuitry may include a digital or analog phase-locked loop having a first frequency divider, a ring oscillator, and an auxiliary phase noise cancellation loop coupled to the ring oscillator. The auxiliary phase noise cancellation loop may include at least a time-to-digital converter, a second frequency divider, an amplifier, and a bandpass filter configured to reject thermal and quantization noise associated with the time-to-digital converter. The first frequency divider may have a first division ratio, whereas the second frequency divider may have a second division ratio that is less than the first division ratio to provide faster phase noise correction.

Ring oscillator phase-locked loop with digital phase noise suppression

A power amplifier and method for operating the same is disclosed. The amplifier includes a number of transistors coupled in series between a power node and a ground node. These transistors include a first transistor having a source terminal coupled to the power node, and a second transistor having its source terminal coupled to a ground node. A subset of transistors is also coupled in series between the first and second transistors. During operation in a first mode, the first and second transistors act as switching transistors, switching according to data received thereby. The subset of transistors, during the first mode, act as cascode transistors. During a second mode of operation, the transistors of the subset act as switching transistors, switching in accordance with the received data.

High efficiency switching power amplifier

A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.

Memory effect reduction using low impedance biasing

An apparatus comprises an amplifier and a pre-distortion circuit coupled to an input of the amplifier. A saturation value of an input signal corresponds to a maximum output power of an output signal of the amplifier. An input target value of the input signal is determined according to the saturation value. The input target value is determined by subtracting an offset from the saturation value or by multiplying a ratio by the saturation value. An average value or an RMS value of the input signal is controlled to be substantially equal to the input target value. A method comprises determining an input target value according to a saturation value, and controlling an input signal according to the input target value.

Pre-distortion based power control

An apparatus includes an antenna, a first transceiver circuit, a second transceiver circuit, a first filter coupled between the antenna and the first transceiver circuit and configured to pass a first signal and attenuate a second signal, and a second filter coupled between the antenna and the second transceiver circuit and configured to pass the second signal and attenuate the first signal. The first signal has a first frequency and the second signal has a second frequency. The first transceiver circuit, the second transceiver circuit, and the first filter are integrated in a system on chip (SOC).

Frequency domain multiplexer

A system including an amplifier circuit configured to amplify an input and generate an output, a bias circuit configured to bias the amplifier circuit, and a feedback circuit configured to generate feedback based on the input and the output, and to adjust the bias of the amplifier circuit based on the feedback to reduce amplitude nonlinearity in the output. A digital pre-distortion circuit is configured to reduce phase nonlinearity in the output.

Power amplifier with wide band AM-AM feedback and digital pre-distortion

A transformer includes a first loops and second loops. The first loops include a first set of input terminals. The first loops include at least three loops that are conductively coupled to each other in series by first crossovers. The second loops include a first set of output terminals. The second loops include at least three loops that are conductively coupled to each other in series by second crossovers. Each of the second conductive loops is inductively coupled to and nested within a respective one of the first conductive loops.

Transformer circuits having transformers with figure eight and double figure eight nested structures

A power detection circuit configured to detect an output power of a radio frequency transmitter. The power detection circuit includes a multiplier circuit configured to multiply a first differential input signal and a second differential input signal. The first differential input signal corresponds to a radio frequency signal to be amplified by the radio frequency transmitter. The second differential signal corresponds to an output signal as amplified by an amplifier of the radio frequency transmitter. A bias circuit is configured to generate a bias signal. A differential amplifier is configured to generate, based on the bias signal and the first differential signal and the second differential signal as multiplied by the multiplier circuit, an indication of the output power of the amplifier of the radio frequency transmitter.

Method and apparatus for detecting an output power of a radio frequency transmitter using a multiplier circuit

An amplifier biasing circuit that reduces gain variation in short channel amplifiers, an amplifier biasing circuit that produces a constant Gm biasing signal for short channel amplifiers, and a multistage amplifier that advantageously incorporates embodiment of both types of amplifier biasing circuits are described. Both amplifier biasing circuit approaches use an operational amplifier to equalize internal bias circuit voltages. The constant Gm biasing circuit produces a Gm of 1/R, where R is the value of a trim variable resistor value. The biasing circuit that reduces gain variation produces a Gm of approximately 1/R, where R is the value of a trim variable resistor value, however, the biasing circuit is configurable to adjust the bias circuit Gm to mitigate the impact of a wide range of circuit specific characteristics and a wide range of changes in the operational environment in which the circuit can be used, such as changes in temperature.

Reduced gain variation biasing for short channel devices

A circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance.

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Mountain View, CA, United States of America

David M Signoff