Intel Corporation

Micron Technology Incorporated

David M Puffer

Altug Koker

Joydeep Ray

Abhishek R Appu

Balaji Vembu

Prasoonkumar Surti

Ankur N Shah

Subramaniam M Maiyuran

Guei-Yuan Lueh

Murali Ramadoss

Aditya Navale

Bryan R White

Vasanth Ranganathan

Kiran Chand Veernapu

Travis T Schluessler

Lakshminarayanan Striramassarma

Pattabhiraman K

Niranjan L Cooray

James A Valerio

David J Cowperthwaite

Hema Chand Nalluri

Kamal Sinha

Aravindh V Anantaraman

Rajesh M Sankaran

Linda L Hurd

Kun Tian

Ingo Wald

Supratim Pal

Suneel G Mitbander

Elmoustapha Ould-Ahmed-Vall

Varghese George

Nikos Kaburlasos

Eric C Samson

Gabor Liktor

Tomer Bar-On

Hugues Labbe

Mike MacPherson

John G Gierach

Valentin Andrei

Stephen Junkins

Sameer Kp

Andrew T Lauritzen

Lyonel Renaud

Satyeshwar Singh

Sanjeev S Jahagirdar

Michael Apodaca

Kai Xiao

Nicolas C Galoppo Von Borries

Mahesh S Natu

Abhishek Venkatesh

Wenyin Fu

Josh B Mastronarde

Bhushan M Borole

Tomasz Janczak

Arthur Hunter, Jr

Eric J Hoekstra

Slawomir Grajewski

Eric J Asperheim

Daren J Schmidt

James Chapple

Kritika Bala

Sarath Kotamreddy

Adam T Lake

Ben J Ashbaugh

Scott R Janus

Changliang Wang

Jeffery S Boles

Devan Burke

Jonathan Kennedy

Brent E Insko

Kurt B Robinson

Brian T Lewis

Yunbiao Lin

Rahul Pal

Vidhya Krishnan

Satyanantha Ramagopal Musunuri

Brandon L Fliflet

Saurabh Tangri

Michael F Cole

Gang Y Chen

Joy Chandra

Siddhartha Chhabra

Zhi Hu Wang

Tomas G Akenine-Moller

Andrew J Herdrich

Blaise B Fanning

Brian K Langendorf

Zhi Jun Wang

Utkarsh Y Kakaiya

Bruce A Young

Daniel Nemiroff

James M Dodd

Aditya Sreenivas

Jim K Nilsson

Pratik M Marolia

Ajaya V Durg

Todd M Witter

Sayantan Sur

Ashok Jagannathan

Marc D Torrant

Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

Multi-render partitioning

Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.

Local memory translation table accessed and dirty flags

An apparatus to facilitate a dynamically scalable and partitioned copy engine is disclosed. The apparatus includes a processor comprising copy engine hardware circuitry to facilitate copying surface data in memory and comprising: a plurality of copy front-end hardware circuitry to generate a plurality of surface data sub-blocks, wherein a number of the plurality of copy front-end hardware circuitry corresponds to a number of partitions configured for the processor, with each partition associated with a single copy front-end hardware circuitry; a plurality of copy back-end hardware circuitry to operate in parallel to process the plurality of surface data sub-blocks to perform memory accesses, wherein subsets of the plurality of copy back-end hardware circuitry are each associated with the single copy front-end hardware circuitry associated with each partition; and a connectivity matrix hardware circuitry to communicably connect the plurality of copy front-end hardware circuitry to the plurality of copy back-end hardware circuitry.

Dynamically scalable and partitioned copy engine

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

Accelerator controller hub

Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.

Graphics processor data access and sharing

A processor unit comprising a first controller to couple to a host processing unit over a first link; a second controller to couple to a second processor unit over a second link, wherein the second processor unit is to couple to the host central processing unit via a third link; and circuitry to determine whether to send a cache coherent request to the host central processing unit over the first link or over the second link via the second processing unit.

Peer-to-peer link sharing for upstream communications from XPUS to a host processor

Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

Scalable I/O virtualization interrupt and scheduling

Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

Multi-tile memory management

One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.

Page faulting and selective preemption

Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

One embodiment provides a parallel processor comprising a memory interface and a processing array coupled with the memory interface. The processing array is configured to address memory accessed via the memory interface via a virtual address mapping and includes circuitry to resolve a page fault for the virtual address mapping, wherein each of the multiple compute blocks is separately preemptable.

Assistance for hardware prefetch in cache access

One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.

Sector cache for compression

Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.

Device memory protection for supporting trust domains

Growing community of inventors

Tempe, AZ, United States of America

David M Puffer