Silicon Graphics, Incorporated

David M Perry

Givargis George Kaldani

Doug Solomon

A method and apparatus for purging data from a middle cache level without purging the corresponding data from a lower cache level (i.e., a cache level closer to the processor using the data), and replacing the purged first data with other data of a different memory address than the purged first data, while leaving the data of the first cache line in the lower cache level. In some embodiments, in order to allow such mid-level purging, the first cache line must be in the &ldquo;shared state&rdquo; that allows reading of the data, but does not permit modifications to the data (i.e., modifications that would have to be written back to memory). If it is desired to modify the data, a directory facility will issue a purge to all caches of the shared-state data for that cache line, and then the processor that wants to modify the data will request an exclusive-state copy to be fetched to its lower-level cache and to all intervening levels of cache. Later, when the data in the lower cache level is modified, the modified data can be moved back to the original memory from the caches. In some embodiments, a purge of all shared-state copies of the first cache-line data from any and all caches having copies thereof is performed as a prerequisite to doing this exclusive-state fetch. Also described is a method and apparatus for converting from a system-level cache line (e.g., in one embodiment, a 128-byte directory-based cache coherence model) to a different processor-level cache line (e.g., in one embodiment, a 64-byte, snoop-based cache-coherence model).

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San Jose, CA, United States of America

David M Perry