Silicon Graphics, Incorporated

David M Parry

Hansel A Collins

Paul Everhardt

Steven C Miller

Michael Brian Galles

Charles E Narad

Daniel E Lenoski

George S Taylor

Greg Chesson

Jon C Gibbons

David B Roberts

A clock edge placement circuit for implementing source synchronous communication between integrated circuit devices. The clock edge placement circuit includes a delay line having an input to receive a clock signal from an external clock source. A corresponding output is included to provide the clock signal to external logic elements. The delay line structure adapted to add a propagation delay to the input, wherein the propagation delay is sized such that the phase of the clock signal is adjusted to control synchronous sampling by the external logic elements. The delay line is adapted to dynamically adjust the delay such that the phase of the clock signal at the output remains adjusted to control synchronous sampling by the external logic as variables affecting the phase of the clock signal change over time. A series of taps are included within the delay line. The delay line uses the series of taps to add a variable delay for adjusting the phase of the clock signal. Each tap is configured to add an incremental delay to the input to generate the variable delay.

Method and system for clock cycle measurement and delay offset

A data synchronizer ( ) receives a data ready signal ( ) at a selector ( ). The selector ( ) selects either the data ready signal ( ) or a delayed version of the data ready signal ( ) in response to a speed select signal ( ) determined according to a clock speed of a receive core clock ( ). The selector ( ) provides a select signal ( ) to a first latch unit ( ) and a second latch unit ( ). The first latch unit ( ) generates a latched select signal (A) that is provided as a receive data valid signal ( ) by a signal generator ( ) in response to a slow clock rate for the receive core clock ( ). The second latch unit ( ) generates a delayed select signal (B) that is used by the signal generator ( ) to remove an extra width inserted into the latched select signal (A) prior to providing the receive data valid signal ( ) in response to a fast clock rate for the receive core clock ( ).

Data synchronizer for a multiple rate clock source and method thereof

The present invention comprises a dynamic skew compensation circuit. The present invention includes a receiver, a plurality of channel inputs built into the receiver, and a delay stack structure coupled to the plurality of channel inputs. The receiver is adapted to accept data from a parallel data transfer cable. The channel inputs couple to each of the individual communications channels which comprise the parallel data transfer cable. The delay stack structure includes a plurality of delay stacks, each coupled to a respective channel input. Each delay stack dynamically selects an additional delay amount for its respective communications channel such that each communications channel of the parallel data transfer cable is deskewed with respect to the others. In so doing, the distances across which data can be received and the speeds at which data is transferred via the parallel data transfer cable is increased.

Method and system for deskewing parallel bus channels

A clock system for a distributed multiprocessor system includes a plurality of local clock circuits and a distribution network. The distribution network includes a plurality of interconnected routers. Each local clock circuit is associated with a processing node of the multiprocessor system. Each local clock circuit generates a global clock source signal, provides the global clock source signal to the distribution network, receives a global clock signal back from the distribution network, and generates a global time value based on a local clock signal and the global clock signal. The router is part of the distribution network of the multiprocessor system. The router receives the global clock source signals from each of the local clock circuits, selects one of the global clock source signals as the global clock signal and provides the global clock signal to the distribution network for distribution to each of the local clock circuits.

Distributed global clock system

Methods and apparatus for optimizing the operation of an instruction pipeline in a computer are disclosed. The methods and apparatus function at both the effective beginning and end of the pipeline. At the pipeline's beginning, a Pipeline Controller monitors the availability of data for various floating point operations. Data is read at either a fast or slow rate, depending on its availability, and instructions are allowed to proceed through the pipeline based on this data availability. At the effective end of the pipeline, the Controller monitors all instructions in the pipeline, notes all potential resource conflicts, and resolves these potential conflicts by either the insertion of an appropriate number of HOLD states or the conclusion that no actual resource competition exists.

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Santa Clara, CA, United States of America

David M Parry