International Business Machines Corporation

David M Onsongo

Dureseti Chidambarrao

David R Hanson

Haining S Yang

John Edward Sheets, Ii

Kirk David Peterson

David Paul Paulsen

Andrew Benson Maki

Werner A Rausch

Benjamin A Fox

Trevor Joseph Timpane

Nathaniel James Gibbs

Kern Rim

Richard Quimby Williams

James Johnson

Steven John Baumgartner

Gregory J Fredeman

Anda C Mocuta

Ricardo Alves Donaton

Tina Jane Wagner

Judith H McCullen

Donald L Jordan

A computer-implemented method includes receiving layout information associated with a circuit design at an extractor, and generating three-dimensional (3-D) heat source grid information based on the layout information, an extracted netlist, and wire information. The method also includes sending the wire information to an electromigration(EM)/current(IR) analyzer, sending the extracted netlist to a circuit simulator, and sending the 3-D heat source grid information to a thermal analysis component. The circuit simulator is configured to generate temperature waveforms and current waveforms based on the extracted netlist. The thermal analysis component is configured to generate heat source information to be provided to the EM/IR analyzer. The method further includes determining, at the EM/IR analyzer, an electromigration risk associated with a wire based on the wire information, the current waveforms, and the heat source information.

Heat source integration for electromigration analysis

A circuit that regulates electrical current flow through an integrated circuit involves a sequencing circuit connected to a clock signal generator, the sequencing circuit configured to, responsive to receiving a clock signal from the clock signal generator, generate a set of sequencing signals that includes a first switching signal, a second switching signal, and a disable signal. The circuit also involves a switching circuit connected to the sequencing circuit, the switching circuit configured to receive the first switching signal and the second switching signal and a current mirror connected to the switching circuit and the sequencing circuit, the current mirror configured to receive an activation signal from a current control logic circuit and to receive the disable signal.

Bias-temperature induced damage mitigation circuit

A method for calibrating resistors on an integrated circuit chip via a daisy chain scheme. The method comprises the step of configuring one or more links of the daisy chain scheme, wherein each of the one or more links comprises one or more master resistors and one or more slave resistors. The method further comprises the steps of calibrating at least one on-chip reference resistor, the one or more master resistors, and the one or more slave resistors via the daisy chain scheme. The method using the daisy chain scheme enables resistance of at least one off-chip reference resistor to be duplicated to multiple distant locations while maintaining a low mismatch error.

Calibrating on-chip resistors via a daisy chain scheme

An FET including a gate conductor overlying a channel has first and second threshold voltages, respectively of a first and a second magnitude. When the second magnitude exceeds the first magnitude, both threshold voltages become effective concurrently. The FET operates responsive to a gate-source voltage between the gate conductor and source in states that include a non-conductive state. When the magnitude of the gate-source voltage is lower than the first and second magnitudes, the source-drain current is negligible. The first conductive state when the magnitude of the gate-source voltage exceeds the first magnitude and is lower than the second magnitude, the source-drain current operates at ten or more times exceeding the negligible value. When the second conductive state exceeds the magnitude of the gate-source voltage and exceeds the first and second magnitude, the state the source-drain current has a second operating value ten or more times higher than the first.

Field effect transistor having multiple conduction states

A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes.

Structure and method for forming a light detecting diode and a light emitting diode on a silicon-on-insulator wafer backside

The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

CMOS diodes with dual gate conductors, and methods for forming the same

A field effect transistor ('FET') is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies a first stress to the first portion of the major surface, and a second liner applies a second stress to the second portion of the major surface. The first and second stresses are each selected from high tensile stress, high compressive stress and neutral stress, with the first stress being different from the second stress. The liners can help to differentiate a first operating current conducted by the first portion of the FET under one operating condition and a second operating current that is conducted by the second portion of the FET under a different operating condition.

Multiple conduction state devices having differently stressed liners

A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.

Silicon/silcion germaninum/silicon body device with embedded carbon dopant

System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search 'buckets' that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).

Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models

A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conduction state field effect transistor ('multi-state FET') having at least one of a source or a drain coupled to the electrically alterable element to apply a current to the electrically alterable element. The multi-state FET has a first threshold voltage and a second threshold voltage, both being effective at the same time, the second threshold voltage being higher than the first threshold voltage. The gate is operable to control operation of the multi-state FET in multiple states including a) an essentially nonconductive state; b) a first or 'low' conductive state when a gate-source voltage exceeds the first threshold voltage, in which the multi-state FET is biased to conduct a relatively low magnitude current for determining the state of the fuse; and c) a second conductive state when the gate-source voltage exceeds the second threshold voltage, in which the multi-state FET is biased to conduct a relatively high magnitude programming current.

Programming and determining state of electrical fuse using field effect transistor having multiple conduction states

An integrated circuit is provided which includes a sensing circuit. In the sensing circuit, a pair of conductors including a first conductor and a second conductor are adapted to conduct a first differential signal having a small voltage difference and a second differential signal having a rail-to-rail voltage difference. A sense amplifier is coupled to the pair of conductors, the sense amplifier being operable to amplify the first differential signal into the second differential signal. The sensing circuit further includes a multiple conduction state field effect transistor or 'multi-state FET' which has a source, a drain, and a gate operable to control conduction between the source and the drain. The multi-state FET has a first threshold voltage and a second threshold voltage which is effective at the same time as the first threshold voltage such that the multi-state FET is operable by the gate voltage to switch between an essentially nonconductive state, a first conductive state when a gate-source voltage applied between a gate and a source of the FET is between the first threshold voltage and the second threshold voltage, and a second conductive state when the gate voltage exceeds the second threshold voltage. The multi-state FET is used to perform an operation included in amplifying the first signal into the second signal by the sense amplifier.

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Newburgh, NY, United States of America

David M Onsongo