Hycom Incorporated

Adc Dsl Systems, Inc.

David M Motley

King Y Cheng

John F Stockman

Andrew M Kameya

Naif D Salman

Robert S Kroninger

Richard Kolbush

Richard W Middlestead

A central office line unit (COLU) for a pulse code modulation (PCM) upstream and downstream system in a universal digital loop carrier (UDLC) includes a hybrid circuit for transmitting/receiving an analog signal to/from a switch. An analog-to-digital converter is provided for receiving the analog signal from the hybrid circuit and converting the analog signal to a converted digital signal. A digital transmission circuit transmits/receives a digital signal to/from a remote terminal. A quantizer is provided for evaluating and processing the converted digital signal so that only valid states of the converted digital signal are transmitted to the digital transmission circuit for transmission to the remote terminal. A receiver is used for receiving the digital signal from the digital transmission circuit and for evaluating and processing the digital signal so that only valid states of the digital signal are outputted from the receiver. A transmitter receives the digital signal from the receiver and equalizes the digital signal. And, a digital-to-analog converter converts the equalized digital signal to a converted analog signal and transmits the converted analog signal to the hybrid circuit, which transmits the converted analog signal to the switch.

PCM upstream and downstream system for universal digital loop carrier

4800 B/S full duplex operation of a frequency-multiplexing modem over the switched telephone network without cancellation is made possible by combining 900-baud, 32-state operation with a combination of analog filtering and raised cosine digital filtering and stop bit robbing.

Frequency multiplexed full duplex 4800 BPS modem

Frequency multiplexed full duplex 4800 bps modem

Filter quality is substantially improved (or complexity substantially reduced) in a digital PSK modem requiring an overall filter characteristic of the percent raised cosine type by using, in both the transmitter and the receiver, a filter having the same percent raised cosine response but at a higher cutoff frequency which satisfies the formula ##EQU1## where f.sub.f is the cutoff frequency (6 db) of the new filter, f.sub.o is one-half the baud rate of the modem, and .alpha. is the percent raised cosine expressed in decimal form.

Raised-cosine filtering for modems

Error multiplication in the differential decoder and descrambler of V.22 bis modems is avoided by replacing the differential coding with forward error correction and single symbol coding. The error syndrome bit of the error corrector is used in establishing phase and timing synchronization by causing the receiver to try all possible combinations of phase and timing, and to lock onto the combination which produces a minimum of error syndrome bits. The descrambler receives the error-free corrected bit stream, whereby the descrambler's inherent error multiplication becomes moot.

Error-correcting modem

A fast learn modem comprising a transmitter for generating a fast learn preamble and applying the preamble to a communication channel and a receiver for receiving the fast learn preamble from the communication channel. The fast learn preamble includes a single impulse and the timing, phase and equalization characteristics of the receiver are adjusted in response to the single impulse so that the receiver can receive and process data.

Single pulse fast learn modem

An apparatus for processing an information signal representative of information and containing phase error. The apparatus includes a detector for detecting the information in the signal and an error signal generator for generating an error signal representative of the error. A phase lock loop makes corrections which tend to reduce the phase error. The gain of the phase lock loop is adjusted in accordance with the error signal to optimize system performance.

Adaptive phase lock loop

A phase tracking network comprising a phase correction network for correcting at least some of the phase error of an input signal to provide a phase corrected signal having components in first and second channels and a detector responsive to the phase corrected signal for providing a detected signal having first and second components in the first and second channels. An error calculator provides a phase correction signal back to the phase correction apparatus which responds to the phase correction signal to correct the phase error of the input signal. The phase error signal contains substantially no noise from the first channel at least when the first component of the detected signal is zero and contains substantially no noise from the second channel at least when the second component of the detected signal is zero. This is accomplished by utilizing the error calculator to provide a first control signal which represents a first fixed value, zero, and a second fixed value when the first component of the detected signal is ideally positive and not zero, ideally zero, and ideally negative and not zero, respectively. The error calculator similarly provides a second control signal for the second component of the detected signal.

Phase tracking network

In a receiver, an analog-to-digital converter is adapted to sample a distorted analog signal to provide a plurality of distorted digital symbols separated in time by a particular interval. In an equalizer, taps are provided with variable multiplying coefficients which sequentially multiply the distorted digital symbols to provide undistorted digital symbols. A timing control network is responsive to variation in one of the multiplying coefficients to control the timing of the converter and hence the duration of the particular interval.

Timing recovery for an automatically equalized data modem

A data transmission system is provided with a double sideband suppressed carrier transmitter and receiver for transferring data between data processing apparatuses. The transmitter and receiver communicate over a telephone line which has physical characteristics which produce delay and attenuation distortion and phase jitter in the transmitted signal. The receiver includes a sampler for converting the transmitted signal into a digital signal, an automatic equalization network for correcting the delay and attenuation distortion, and a phase correction network compensating for frequency offset, phase offset, and phase jitter. The phase corrected and equalized signal is then detected and introduced to the data processing apparatus. An error signal calculator is responsive to the phase corrected signal and the detected signal to provide a system error signal for automatically updating the functions of the equalization and phase correction networks in accordance with the characteristics of the incoming signal. A timing control network which is also responsive to the system error signal, provides a timing error signal for correcting the sampling rate of the sampler. Filters in the transmitter and receiver provide the system with partial response signaling so the bandwidth of the system can be minimized, and even telephone lines of poor quality can accommodate a full duplex secondary channel for system control.

Digital data receiver with automatic timing recovery and control

In a system for transmitting information between first and second data processing apparatuses, a signaling scheme provides a digital data signal with in-phase components and quadrature components which define a plurality of vectors. The vectors, when plotted on a graph having an abscissa and an ordinate, each have a minimum separation distance defined by the radius of a circle having its center at the tip of the associated vector. The circles of the vectors, which are aligned in rows substantially parallel to the abscissa or the ordinate of the graph, are tangential to the adjacent circles. Boundary areas associated with the respective vectors are defined by boundary lines extensions of which pass through points defined by the vector components. This signaling scheme minimizes vector magnitude, associated with minimum power, while maximizing vector separation distance, associated with reduced detection error.

Data transmission system using optimal eight-vector signaling scheme

A demodulator for detecting first and second frequencies in an analog input signal includes a limiter providing first pulses having a short duration in response to the first frequency and having a long duration in response to the second frequency. A first counter provides a first reference signal including second pulses, and a second counter provides a second reference signal including third pulses. Logic means responsive to the second and third pulses provide a signal including fourth pulses during periods corresponding to the first frequency and a signal including fifth pulses during periods corresponding to the second frequency. An up-down counter is responsive to the fourth pulses to provide a first output signal and responsive to the fifth pulses to provide a second output signal. The fourth and fifth pulses have frequencies and durations providing the counter with substantially equal counting rates during the periods corresponding to the first and second frequencies of the analog signal.

Frequency shift key demodulator

A phase tracking network for correcting an undesirable first phase angle of a first signal, includes an error calculating circuit responsive to partial response data signals to provide a phase error signal. Filter means adapted to be coupled to the error calculating circuit is responsive to the linear and nonlinear characteristics of the phase error signal to provide a second phase angle in a second signal. A phase correction network coupled between the filter means and the error calculating circuit is responsive to the second phase angle in the second signal to correct the first phase angle in the first signal.

A receiver includes means for sampling and noncoherently demodulating a received signal to provide digital symbols in each of a first and second channel. An equalization network equalizes the incoming signal and a phase correction network corrects the phase of the equalized signal. In response to the transmission of a preamble in the first channel, a fast learn network derives the phase error by determining the arc tangent of a quotient formed by dividing the signal in the first channel by the signal in the second channel. A course phase jump can be made to insure that the arc tangent is not greater than unity. The timing error of the sampling means can be derived by determining the arc tangent of a quotient formed by dividing the present digital symbol in the one channel by the preceding digital symbol in the one channel. In response to an impulse in the preamble, the lead-in samples of an impulse response can be stored while the phase error is computed from the major sample; then the phase of the lead-in samples can be corrected. Equalization coefficients can be derived from the phase corrected impulse response samples. With this apparatus, in accordance with the preferred method of the present invention, the receiver can be adapted to receive normal data in less than thirty milliseconds.

Ultrafast adaptive digital modem

An automatic digital modem receiving an input analog signal samples the input signal to provide a random multilevel data signal. This multilevel signal is equalized and phase corrected so that the characteristics of the modem are substantially synchronized with the characteristics of the input analog signal. A system error signal which is responsive to the random multilevel data signal is averaged to provide a synchronization quality signal. When the synchronization quality signal degrades to a predetermined magnitude, a restart signal adjusts the sampling, the equalization, and the phase correction of the modem to reduce the magnitude of the synchronization quality signal. The associated method includes the steps of adjusting only the phase correction of the modem for a particular interval of time and then jumping the sampling of the modem if the synchronization quality signal has not been reduced below the first predetermined magnitude.

Growing community of inventors

Santa Ana, CA, United States of America

David M Motley