Xilinx, Inc.

Other

David M Mahoney

Mohsen Hossein Mardi

Suresh Ramalingam

Stephen M Trimberger

Jaspreet Singh Gandhi

Martin L Voogel

Gamal Refai-Ahmed

James Karp

Hong Shi

Henley Liu

Ivor G Barber

Zhi-min Ling

Tien-Yu Lee

Feng Wang

Siow Chek Tan

Joseph M Juane

Brian Sadler

Owais E Malik

Tarek Eldin

Cosimo Cantatore

Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.

Method and apparatus of package enabled ESD protection

Examples described herein provide for testing of a test socket using multiple insertions to a contact resistance (CRES) test system. In an example, the test socket is placed in a first orientation on an interface board electrically connected to a test system. Using the test system and through the interface board, a first subset of probes of the test socket is tested while the test socket is in the first orientation on the interface board. The test socket is placed in a second orientation different from the first orientation on the interface board. Using the test system and through the interface board, a second subset of probes of the test socket is tested while the test socket is in the second orientation on the interface board. At least some probes of the second subset of probes are different from the first subset of probes.

Multiple insertion testing of test socket

A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In one example, the IC die of the chip package assembly is disposed on a first surface of the substrate. The PMIC die has a first surface having outputs electrically coupled to the second surface of the IC die. The PMIC die also has a second surface facing away from the first surface. The second surface of the PMIC die has inputs that are electrically coupled to the first surface of the substrate.

Chip package assembly with power management integrated circuit and integrated circuit die

An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress includes a plurality of pusher pins. The plurality of pusher pins have tips extending from a bottom surface of the workpress. Each of the plurality of pusher pins is configured to apply an independent and discrete force to the chip package assembly disposed in the socket.

Integrated circuit package testing system

An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress is positioned over the socket and has a bottom surface that is dynamically conformable to a multi-planar top surface topography of the chip package assembly.

Chip package test system

Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

Testing system for lid-less integrated circuit packages

In a transmission line via structure, a plurality of sub-structures are stacked in a via through the substrate along a longitudinal axis thereof. Each of the sub-structures includes a center conductor portion, an outer conductor portion, and at least one dielectric support member. The center conductor portion extends along the longitudinal axis. The outer conductor portion is disposed around the center conductor portion. The dielectric support member(s) separate the outer conductor portion and the center conductor portion and provide a non-solid volume between the outer conductor portion and the center conductor portion. Conductive paste is disposed between the center and outer conductor portions of successive ones of the plurality of sub-structures to form an outer conductor and a center conductor.

Transmission line via structure

One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip.

Corner structure for IC die

Disclosed is a contactor interconnect in an integrated circuit device test fixture comprises a plurality of contactor pins enabled to provide electrical contact with the contact points of an integrated circuit device, the contactor pins being mounted in the test fixture; and an electrical circuit coupled to two or more of the contactor pins of the test fixture, wherein the electrical circuit is isolated from other contactor pins of the plurality of contactor pins and wherein the electrical circuit is coupled to the two or more contactor pins by an electronically direct pathway.

High-speed contactor interconnect with circuitry

A socket for an integrated circuit is disclosed. The socket comprises a main body portion having a plurality of holes extending between a top surface and a bottom surface; an overlay positioned adjacent to the main body portion and having a plurality of holes corresponding to the plurality of holes of the main body portion, wherein the overlay comprises a plurality of conductors between holes; and a plurality of contact elements positioned in predetermined holes of the main body portion. A method of providing a connection in a socket is also disclosed.

Socket for an integrated circuit and a method of providing a connection in a socket

Embodiments of the present invention provide improved circuit board stiffeners. In one embodiment the present invention includes a circuit board stiffener comprising a lower stiffener piece having a first lower surface for abutting an upper surface of a test system and a first upper surface, and at least one upper stiffener piece having a second lower surface for abutting the first upper surface of the lower stiffener piece and a second upper surface for attaching to a circuit board.

Circuit board stiffener

A test system configuration is provided to enable testing of integrated circuit (IC) packages. The test system includes a test controller, an interface apparatus including a PC board with lines connecting the test controller to contact areas for contacting the IC packages and a handler for supporting the IC chips and interface apparatus to maintain electrical connections during testing. The handler includes docking plates for attaching to the PC board to provide a guide for the IC packages that are inserted in openings of the docking plates to align contacts of the IC packages and PC board. The docking plates are configured to provide quad (four) and octal (eight) test sites, with either the quad or octal docking plate mating to the same PC board and being supported in the same handler system. An alignment frame for mounting either the quad or octal docking plate is further provided as part of the handler.

Octal/quad site docking compatibility for package test handler

A standardized test head assembly for testing a plurality of integrated circuit dice each having a different bonding pad footprint, the test head assembly including an arrangement of probe holes defined by a predetermined configuration of contact positions, wherein the predetermined configuration defines each of the different bonding pad footprints so that during testing the probe holes align with a subset of the bonding pads for each of the different bonding pad footprints.

Methods for standardizing a test head assembly

The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point ('PIP') in the line segment is tested by generating routes from a first logic port through the original line segment and PIP, through all PIPs, adjacent to the original PIP to the opposite logic port. Routes through all PIPs adjacent to the PIPs in the line segment from the first logic port to the second logic port, and from the second logic port to the first logic port, are tested to isolate the fault in the line segment.

Method of automatic fault isolation in a programmable logic device

Die probing devices can include multiple sets of probe wires, where certain probe wires correspond to test pads and other correspond to bond pads. The probe wires can be electrically coupled to each other using either a space transformer or a probe card, to provide appropriate continuity. Probe wires can generally be arranged in numerous different patterns depending upon (for example) pad layout, wire configuration, wire type, and probe head design/manufacturing constraints.

Growing community of inventors

Gilroy, CA, United States of America

David M Mahoney