Oracle International Corporation

Sun Microsystems, Inc.

David M Kahn

John R Feehrer

Hugh R Kurth

Patrick Stabile

John Johnson

Tayfun Kocaoglu

Ashley N Saulsbury

Ricky C Hetherington

Rahoul Puri

Francesco DiMambro

Gregory Charles Onufer

Julia D Harper

Brian McGee

Robert Dickson

Matthew Cohen

Alan Adamson

Bruce J Chang

Sumanth R Kamatala

Sriram Jayakumar

Asif H Haswarey

Anil Umarshi Visariya

Robert G Sheldon

Carl F Humphreys

Mark Kanda

Aruna Jayakumar

An apparatus and method for controlling a device with shared hardware resources to provide separate execution environments for control and data functions are disclosed. A processor may be configured to generate a first request to access control functions of the device in response to execution of a first thread, and generate a second request to access data functions of the device in response to execution of a second thread. A communication unit may send first indicative of the first request and second data indicative of the second request to the device via first and second ports, respectively.

Separation of control and data plane functions in SoC virtualized I/O device

Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Aggregation of interrupts using event queues

An input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive interrupts or messages from a corresponding endpoint device. A given communication unit may be further configured to synthesize a virtual address from the received message, translate the synthesized virtual address to a real address, and then translate the real address to a physical address. The interface unit may be configured to send an interrupt dependent upon the physical address.

Virtualizing input/output interrupts

The disclosed embodiments provide a system that validates message-signaled interrupts. During operation, the system receives a message-signaled interrupt from a requesting device. This message-signaled interrupt includes an interrupt vector that identifies an interrupt, and is accompanied by an identification tag that identifies the source of the interrupt. The system uses the interrupt vector to access a stored tag from a tracking mechanism that associates source devices with their assigned interrupt vector(s). The system then compares the identification tag and the stored tag to validate the message-signaled interrupt.

Validating message-signaled interrupts by tracking interrupt vectors assigned to devices

A processor employing device-specific memory address translation. In one embodiment, a processor may include a device interface configured to receive a memory access request from an input/output (I/O) device, where the request specifies a virtual memory address and a first requestor identifier (ID) that identifies the I/O device. The processor may also include an I/O memory management unit coupled to the device interface and configured to determine whether a virtual-to-physical memory address translation corresponding to the virtual memory address is stored within an I/O memory translation buffer. The I/O memory management unit may be further configured to determine whether a second requestor ID stored within the I/O memory translation buffer and corresponding to the memory address translation matches the first requestor ID. If the first and second requestor IDs do not match, the I/O memory management unit may disallow the memory access request and to signal an error condition.

Processor and method for device-specific memory address translation

An enhanced VPD structure includes a type field to indicate whether a particular property is a general property to be associated with an interface card or other computer system component, or a device- or function-specific property to be associated with one or more devices or functions. The enhanced VPD structure also includes fields for identifying the device(s) and/or function(s) to which a device- or function-specific property applies, along with the value of the property, a data type and length of the property, and a meaningful name of the property. The enhanced VPD structure may be accessed during system boot, during hot-swapping of an interface card or other component, or at other times.

Enhanced VPD (Vital Product Data) structure

Growing community of inventors

Princeville, HI, United States of America

David M Kahn