Freescale Semiconductor,inc.

David M Gonzalez

James R Griffiths

Elie A Maalouf

An electronic circuit includes an illustrative low voltage CMOS power on reset circuit. The electronic circuit can comprise a power on reset circuit coupled between a supply voltage terminal and a signal node. The illustrative power on reset circuit comprises a voltage detector coupled to the supply voltage terminal which is configured to track CMOS thresholds and deactivate when supply voltage reaches a level for proper operation of CMOS logic.

Low voltage CMOS power on reset circuit

A disclosed RF circuit includes a power amplifier that produces an RF output signal, a detector to generate a detector signal indicative of a power of the RF output signal, and an offset unit to produce an offset signal that indicates low supply voltage conditions. The power of the RF output signal is reduced, at least in part, by a control signal reflecting a combination of the detector signal and the offset signal. The circuit may include a transmitter to provide an RF input signal to the power amplifier. The transmitter may receive the control signal and adjust a power of the RF input signal based on the control signal. The detector may produce a control current indicative of the RF output signal power. The offset unit produces the offset signal based on a difference between the supply voltage and a nominal supply voltage value.

RF circuit with control unit to reduce signal power under appropriate conditions

A power amplifier for use in a radio frequency (RF) transmitter or other device exhibits improved protection from voltage standing wave ratio (VSWR) issues emanating from avalanche currents. The amplifier circuit includes a power transistor having a base terminal, and a mirror transistor having a collector terminal and a base terminal. The base terminal is coupled to the collector terminal of the mirror transistor to thereby provide a bias current to the base terminal of the mirror transistor. The base terminal is also coupled to the base terminal of the power transistor to thereby form a base bias feed node for a current mirror arrangement. A static or variable impedance is coupled to the base bias feed node to sink current and to thereby maintain the proper bias current at the base terminal of the mirror transistor to thereby continue operation of the mirror transistor while avalanche conditions exist.

Power amplifiers having improved protection against avalanche current

Systems and methods are described for improving the startup linearization of a power amplifier. A bias network is provided to generate a bias signal during amplifier startup, and the amplifier is configured to produce an output signal in response to the input signal and the bias signal. A variable impedance is provided to couple the input signal and the output signal in parallel with the amplifier. A controller is configured to apply a weighting function to the variable impedance over at least a startup phase of the amplifier system. By applying a non-linear or other weighting function to the variable impedance during startup, the gain of the amplifier can be controlled to thereby extend a time period over which the output power of the amplifier increases in a generally linear manner toward an operating level.

Power amplifiers having improved startup linearization and related operating methods

An RF transmitting device () includes an RF amplifier () formed having components formed on a common semiconductor substrate (). RF amplifier () includes MOS transistors () and () and an RF choke () stacked between a ground node () and a Vnode (). Transistors () and () are directly connected together and are biased by a control terminal bias network () so that the voltages appearing across their conduction terminals are about equal. Control terminals () and () of transistors () and () are driven by in-phase versions of an RF input signal ().

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Mesa, AZ, United States of America

David M Gonzalez