Coventor, Inc.

Lam Research Corporation

David M Fried

Kenneth B Greiner

Daniel Faken

Stephen R Breit

William J Egan

Anshuman Kunwar

Mattan Kamon

Michal Danek

Atashi Basu

Kapil Umesh Sawlani

Anand Chandrashekar

Yang Pan

Saravanapriyan Sriraman

Dongyao Li

Michael Bowes

Rich Wise

Jiangjiang Gu

Vasanth Allampalli

Yiguang Yan

Daniel Sobieski

Mark J Stock

Emily Ann Alden

A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for performing key parameter identification, process model calibration and variability analysis is discussed.

System and method for performing process model calibration in a virtual semiconductor device fabrication environment

A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for performing process window optimization is discussed.

System and method for process window optimization in a virtual semiconductor device fabrication environment

Cable machine accessory

Methods, systems, and computer programs are presented for determining the recipe for manufacturing a semiconductor with the use of machine learning (ML) to accelerate the definition of recipes. One general aspect includes a method that includes an operation for performing experiments for processing a component, each experiment controlled by a recipe, from a set of recipes, that identifies parameters for manufacturing equipment. The method further includes an operation for performing virtual simulations for processing the component, each simulation controlled by one recipe from the set of recipes. An ML model is obtained by training an ML algorithm using experiment results and virtual results from the virtual simulations. The method further includes operations for receiving specifications for a desired processing of the component, and creating, by the ML model, a new recipe for processing the component based on the specifications.

Determination of recipes for manufacturing semiconductor devices

A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology measurement data from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

System and method for predictive 3-D virtual fabrication

Computer implemented methods and computer program products have instructions for generating transfer functions that relate segments on lithography photomasks to features produced by photolithography and etching using such segments. Such methods may be characterized by the following elements: (a) receiving after development inspection metrology results produced from one or more first test substrates on which resist was applied and patterned using a set of design layout segments; (b) receiving after etch inspection metrology results produced from one or more second test substrates which were etched after resist was applied and patterned using said set of design layout segments; and (c) generating the transfer function using the set of design layout segments together with corresponding after development inspection metrology results and corresponding after etch inspection metrology results.

Resist and etch modeling

System and method for key parameter identification, process model calibration and variability analysis in a virtual semiconductor device fabrication environment

A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

System and method for performing a multi-etch process using material-specific behavioral parameters in a 3-D virtual fabrication environment

Provided herein are systems and methods for optimizing feature fill processes. The feature fill optimization systems and methods may be used to optimize feature fill from a small number of patterned wafer tests. The systems and methods may be used for optimizing enhanced feature fill processes including those that include inhibition and/or etch operations along with deposition operations. Results from experiments may be used to calibrate a feature scale behavioral model. Once calibrated, parameter space may be iteratively explored to optimize the process.

Fill process optimization using feature scale modeling

A virtual fabrication environment for semiconductor device fabrication that determines a lowest lithography exposure dose range in which one or more defects are still reparable by deposition and etch operations is discussed. Further techniques for repairing line edge roughness caused by lithography are described.

System and method for determining dimensional range of repairable defects by deposition and etching in a virtual fabrication environment

Modeling of electrical behavior during the virtual fabrication of a semiconductor device structure is discussed. Electrical behavior occurring in a designated region of a semiconductor device structure may be determined during the virtual fabrication process. For example, resistance or capacitance values may be determined within a modeling domain of interest.

System and method for electrical behavior modeling in a 3D virtual fabrication environment

Predictive 3-D virtual fabrication system and method

The modeling of a DSA step within a virtual fabrication process sequence for a semiconductor device structure is discussed. A 3D model is created by the virtual fabrication that represents and depicts the possible variation that can result from applying the DSA step as part of the larger fabrication sequence for the semiconductor device structure of interest. Embodiments capture the relevant behavior caused by polymer segregation into separate domains thereby allowing the modeling of the DSA step to take place with a speed appropriate for a virtual fabrication flow.

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South Salem, NY, United States of America

David M Fried