Supercomputer Systems Limited Partnership

Sun Microsystems, Inc.

Silicon Graphics, Incorporated

Cray Research, Inc.

David M Cox

Jon A Masamitsu

Robert E Strout, Ii

David A Seberger

Timothy J Cramer

George A Spix

Don A Van Dyke

Diane M Wengelski

Gregory G Gaertner

Keith J Thompson

James C Rasbold

Kelly T O'Hair

Linda J O'Gara

Ashok Chandramouli

Richard E Hessel

Steve S Chen

David M Barkai

Jeremiah D Burke

Mark D Johnson

Giacomo G Brussino

Stuart W Hawkinson

Steven G Oslon

David R Wallace

Serguei L Wenitsky

Serguei V Morosov

An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes

Apparatus, methods and computer program products are disclosed that enable a compiler to generate efficient code to access stack registers on a register stack. The invention operates by transforming a three-operand instruction, within a compiler's intermediate representation, to one or more fewer-than-three-operand instructions. The invention also transforms the instruction's operand addressing from an access to a pseudo-named register to an access to a stack register through stack offset into a register stack. The invention also determines the register stack state at each instruction responsive to register stack permutations and maps the stack offset accordingly for each subsequent access to a stack register.

Method, apparatus and computer program product for optimizing registers

On a tightly coupled multiprocessor computer system, the multiple parallel regions of a multithreaded applications program can execute simultaneously as multiple threads on a plurality of processors. Furthermore, a plurality of multithreaded programs may run simultaneously. The current invention uses an efficient system to schedule and reschedule processors to run these multiple threads. Scheduling is integrated at two levels: at the first level, processors are assigned processes. At the next level, processes are assigned threads. Increased efficiency is achieved by this integration and also by the formation of processes with destructible context. It makes use of shared storage to indicate the process request level and the control state for each parallel region.

Dual level scheduling of processes to multiple parallel regions of a

System and method for controlling a highly parallel multiprocessor using

A modular compilation system that utilizes a fully integrated hierarchical representation as a common intermediate representation to compile source code programs written in one or more procedural programming languages into an executable object code file. The structure of the integrated common intermediate representation supports machine-independent optimizations, as well as machine-dependent optimizations, and also supports source-level debugging of the executable object code file. The integrated hierarchical representation (IHR) is language independent and is shared by all of the components of the software development system, including the debugger.

Computer with integrated hierarchical representation (IHR) of program

A method for representing scalar data dependencies for an optimizing compiler wherein a global scalar data dependence graph is created to represent all of the scalar objects in an entire program. The scalar data dependencies are represented as three chains: a use-definition chain (ud); a definition-use chain (du) or a definition-definition chain (dd), and is created for the entire program and is maintained during the entire compilation or assembly of the program. The method for determining scalar data dependences for the entire program starts by analyzing the scalar data dependences within each basic block, in a single pass, processes all definitions and uses of all non-array data objects in the basic block, including simple variables and complex data objects such as records, unions, pointers and procedure calls in the presence of aliasing. From these objects, information is collected, such as whether the data objects are upwardly or downwardly exposed, pointers, pointer aliases, aggregate objects, array objects, uses, definitions; whether they are calls, indirect uses, or indirect definitions.

Method for representing scalar data dependences for an optimizing

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Livermore, CA, United States of America

David M Cox