Eastman-kodak Company

David M Charneski

Edward P Lawler

John Thomas Compton

James D Shaw

Herbert J Erhardt

Kenneth D Kieffer

Eugene M Petilli

William F DesJardin

Richard B Brolly

James I Hackett

John J Uebelacker

Mark D Brown

Wayne W Hintz

Richard A Wanzenried

Jay E Endsley

A timing generator for an electronic image sensor includes one or more memory based tables for controlling timing events that occur within one or more different types of image sensor lines, and one or more memory based tables for controlling timing events that occur within one or more different types of image sensor frames.

Timing generator for electronic image sensor with tables that control line and frame timing

The present invention includes a system that has been developed to vary the starting and stopping of a pulse train of arbitrary phase without glitches, spurious pulses, or spurious change in duty cycle. This is accomplished by a system for generating a gated periodic waveform, the system includes a generator for generating a periodic waveform of adjustable phase; a device for providing a delayed enable signal based on the phase of the periodic waveform so that the gated periodic waveform can be started and stopped without creating undesirable changes in the gated periodic waveform; and a logic element for generating a gated periodic waveform based on the delayed enable signal and the periodic waveform of adjustable phase.

Enabling method to prevent glitches in waveform of arbitrary phase

An imaging device for generating an image signal includes an image sensing device for producing an image signal subject to one or more clock signals and a circuit for generating one or more of the clock signals, wherein the clock signal generating circuit is responsive to a programmable input signal for adjusting a duty cycle of at least one of the clock signals. In particular, by clocking two recirculating shift registers out of phase and parallel loading them with a programmable bit pattern to produce the output clock signals, the frequency of an input clock that is required to produce the output clock signals can be reduced by half.

Programmable clock generator for an imaging device

A bus interface device for an application specific integrated circuit handles more than two different clock frequencies and allow for real time switching between the clock frequencies by subsystems of the application specific integrated circuit. In a preferred embodiment, a master state machine is provided that includes a plurality of control input lines and a plurality of control output lines, and a plurality of synchronizing state machines each coupled to one of the control output lines of the master state machine and to a separate clock frequency line. The master state machine, based on signals applied to the control input lines, selectively enables the synchronizing state machines to supply the different clock frequencies to the subsystems of the application specific integrated circuit.

Asic bus interface having a master state machine and a plurality of

A method for organizing and addressing memory of a digital video image is provided for one and two dimensional image processing using fast page mode accessing of memory, and also for displaying composite digital video images. A DRAM (12) is mapped to address locations storing segmented memory, non-segmented memory, line pointer tables, and horizontal description tables. The lines of a digital image are organized in DRAM (12) in either segmented memory or non-segmented memory. For segmented memory, each line of the image is broken up into equal line segments of pixels. Vertically aligned columns of line segments in the image are then stored in one or more rows of the DRAM (12). For non-segmented memory, each line is stored in a format where rows of DRAM (12) each represent a line of image data. To provide a means of locating the lines of the image, a line pointer table is stored in the DRAM (12) having entries corresponding to the location in memory of the start of each line of the image, and an indicator in each entry indicating whether a line is segmented or non-segmented. Two dimensional processing of an image in segmented memory is facilitated by fast page mode accessing since both vertical and horizontal pixel information is obtainable in a single row address of DRAM (12). In addition, a horizontal description table provides a means of displaying a composite image without forming the composite image in DRAM (12). Each composite image is divided into zones of rectangular pixel regions, and then separated into sets of lines having one or more zones. For each set of lines, a horizontal description table describes how the pixels in the zones for that set are to be displayed.

Memory organizing and addressing method for digital video images

There is disclosed dispensing apparatus using a container for liquid, the apparatus comprising pressurizing means for aspirating liquid into the container, and for pressurizing liquid within the container to dispense the liquid. To control the ambient pressure of the atmosphere above the liquid within the container, system control means and a method of control are provided. Such means and the corresponding step of the method comprise

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Hilton, NY, United States of America

David M Charneski