International Business Machines Corporation

David M Brooks

Pradip Bose

Stanley Everett Schuster

Peter William Cook

Michael K Gschwind

Alper Buyuktosunoglu

Philip George Emma

Vijayalakshmi Srinivasan

David H Albonesi

A method and structure of reducing power consumption in a microprocessor includes at least one storage structure in which the activity of the storage structure is dynamically measured and the size of the structure is controlled based on the activity. The storage structure includes a plurality of blocks, and the size of the structure is controlled in units of block size, based on activity measured in the blocks. An exemplary embodiment is an adaptive out-of-order queue.

Adaptive issue queue for reduced power at high performance

An integrated circuit (IC) including unit power control, leakage reduction circuit for controllably reducing leakage power with reduced LdI/dt noise in the IC and, an activity prediction unit invoking active/dormant states in IC units. The prediction unit determines turn on and turn off times for each IC unit. The prediction unit controls a supply voltage select circuit selectively passing a supply voltage to a separate supply line at the predicted turn on time and selectively blocking the supply voltage at the predicted turn off time.

Processor with low overhead predictive supply voltage gating for leakage power reduction

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Newark, DE, United States of America

David M Brooks