Agere Systems Inc.

Other

David M Boulin

Isik C Kizilyalli

Nace Layadi

Reginald Conway Farrow

Masis Mkrtchyan

Hugo Fernando Safar

The specification describes a plastic overmolded package for high power devices that has a very low lead count, typically fewer than eight, and in a preferred embodiment, only two. The leads occupy essentially the same linear space as the multiple leads in a conventional package and thus have a wide-blade configuration. To improve mechanical integrity, the leads in the package are provided with retention slots to add back the equivalent of the plastic joints in the spaces that were eliminated due to the wide-blade design. The retention slots extend in the width dimension of the leads.

Leadframe designs for plastic overmold packages

A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Multi-layered semiconductor structure

A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Method of forming an alignment feature in or on a multi-layered semiconductor structure

Method of forming an alignment feature in or on a multilayered semiconductor structure

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Lebanon, NJ, United States of America

David M Boulin