3com Corporation

L3harris Technologies, Inc.

Other

David M Arnesen

Harrison Killian

Shayne Messerly

Christian B Schlegel

L Andrew Gibson

David Moore

Spiro Poulis

Gerald A Wilson

Nicholas T Yaskoff

Marc Padilla

Eric P Mitchell

Jeffrey A Hanline

Connie D York

Richard A Kunz

Systems and methods for mitigating the effect of in-band interference. The methods comprise: receiving a signal comprising at least one interfering signal component; generating a soft value for each symbol in at least one interfering signal component; and using the soft values to cancel at least one interfering signal component from the signal to mitigate the effect of interference. The soft value represents a most likely value for the symbol which is obtained by: determining a probability metric between an actual value of the symbol and each of a plurality of possible symbol values using a scaling value representing an estimate of the noise level in the signal received by the device; generating current local probabilities for the plurality of possible symbol values using the probability metric; and using the current local probabilities to determine the soft value.

System and method implementing soft-decision based excision cancellation technology

A radio frequency (RF) communications system may include a first RF node that transmits data, including a new frequency of operation, and a sequence of pilot symbols spread with a complex spreading code sequence. A second RF node may receive an incoming signal from the first RF node and perform despreading for N sample offset delays to generate N despreading sequences for the sequence of pilot symbols. The second RF node may perform a cross-correlation to select a desired despreading sequence from the N despreading sequences, determine a phase offset and timing offset, process the incoming signal based upon the desired despreading sequence, phase offset and timing offset, and switch to the new frequency of operation.

Radio frequency (RF) communications system having RF nodes that determine a despreading sequence and phase and timing offsets for frequency agility

A system for a sliding-window transform with integrated windowing is described. The system provides a Direct Fourier Transform kernel with an integrated windowing filter having a desired number of stages. In one embodiment, the windowing filter is a lowpass filter. In one embodiment, the lowpass filter has a rectangular filter transfer characteristic. The DFT includes a complex multiplier. A first portion of the windowing filter is provided before the complex multiplier and can be implemented using real arithmetic. A second portion of the windowing filter is provided after the complex multiplier and is implemented using complex arithmetic. In one embodiment, the filter weights of the second portion of the windowing filter are unity and thus no multiplier is needed for the filter weights in the second portion of the windowing filter.

Sliding-window transform with integrated windowing

A system and method for providing a shortened DSP reset pulse to cause a modem to reset and enter a sleep mode as soon as possible after receipt of an external reset pulse issued by a host. A reset controller detects the external reset pulse, issues a separate reset pulse to the modem, monitors the modem's clock and then terminates the separate reset pulse after a prescribed duration. The prescribed duration is determined by the minimum time required by the DSP to reset. The invention is embodied in a modem connected to an external controller. The modem includes a DSP having a reset terminal and a clock. The DSP begins performing a reset upon a first signal applied to its reset terminal and causes the modem to enter a sleep-mode after a second signal is applied to its reset terminal. The external controller is capable of transmitting an external signal. The reset controller in the modem has a counter and an output node. The counter is connected to the clock and provides a counter output signal upon receipt of a predetermined number of cycles of the clock. The counter initiating generally concurrent with receipt of the external signal. The output node is connected to the reset terminal of the DSP and to the output counter. The output node provides a first signal to the DSP generally concurrent with receipt of the external signal and a second signal generally concurrent with receipt of the counter output signal.

System and method in a modem for providing a shortened reset pulse upon receipt of an external reset pulse

The present invention increases data transfer rate and reduces interrupt latency while avoiding a concomitant increase in interrupts to the host, by pacing the data flow between the UART and DSP using burst modes and wait modes.

System and method for data pacing

The high throughput UART to DSP interface (UDIF) maintains UART functionality while integrating dual Transmit (Tx) and Receive (Rx) FIFO buffers that are optimized for more efficient interaction with their respective I/O processors. The portion of the interface design interacting with the DSP, the UDIF, provides several unique Status, Informational, and Control registers that lower the DSP overhead required for many of the basic modem functions. The UDIF design also performs parity add, parity strip, and character echo functions, traditionally performed at a high overhead cost by the DSP. These functions are more efficiently preformed by hardware implementations than by the software routines executed by the DSP. More burdensome command functions like escape, AT, and flow control commands can also be implemented through hardware implementations to reduce processor overhead.

High throughput UART to DSP interface having Dual transmit and receive FIFO buffers to support data transfer between a host computer and an attached modem

A method and apparatus for interconnecting via a serial bus a master processor and a co-processor having directly interfaceable parallel interfaces thereby accommodating the remote location of the co-processor from the master processor. The master processor interfaces with a serial bus interface for converting the parallel interface of the master processor into a serial interface forming a serial bus including a serial data out signal, a serial data in signal, a serial clock signal and a frame sync signal. The serial bus interfaces with the remote module having the co-processor located therein. The serial bus interfaces directly with an interface controller for converting the serial information back to a parallel format compatable with the requirements of the co-processor's parallel interface. The interface controller is further capable of generating control signals such as resets and general purpose outputs when directed by the master processor and reading status of the co-processor when also directed by the master processor. Testing functionality is also included for specific incorporation of an ISDN-specific I/O interface device functioning as the co-processor.

Method and system for interfacing parallelly interfaced devices through

An apparatus and method for facilitating interaction during a communication session between an analog modem and a terminal adapter for conveying digital alert tones and control data therebetween is provided. The embodiments provide for a collateral digital communication path between a microcontroller of an analog modem and a microcontroller of a terminal adapter for selectively relaying digital alert tones and control data therebetween. One embodiment utilizes a cellular interface of an analog modem for tapping and evaluating information for the presence of control data. Upon successful identification of control data, the microcontroller of a terminal adapter is notified and the specific control data detected in identified. By providing a method of apparatus for digitally relaying control data, accuracy of identification of control data by a terminal adapter is enhanced by foregoing needless signal transformation and retransformation.

Growing community of inventors

West Jordan, UT, United States of America

David M Arnesen