Honeywell G.m.b.h.

Honeywell International Inc.

David Lyle Kirk

Jay William Gustin

Elliott H Rachlin

Ananthapadmanabha Krishnamurthy

Robert L Spiesman

Sameer D Manikfan

Michael L Hodge

Elliott Rachlin

A method for bus bridging includes providing a bus interface device that is coupled between at least one module bus and at least one advanced extensible interface (AXI) bus for translating bus requests between the module bus and the AXI bus. The bus interface device includes logic. The logic is configured to receive a read/write (R/W) request that is one of a module bus protocol R/W request and an AXI bus protocol R/W request and to buffer the R/W request to provide a buffered R/W request. The logic translates the buffered R/W request to a first AXI protocol conforming request if the buffered R/W request is the module bus protocol R/W request and translates the buffered R/W request to a first module bus protocol conforming request if the buffered R/W request is the AXI bus protocol R/W request. The translated requests are transmitted to their respective bus.

Bus bridge for translating requests between a module bus and an axi bus

A method includes transmitting, by a first processing device, a signal to a second relay processing device. The signal includes a message for the second relay processing device to transmit a read command and/or a write command to an I/O device that is not accessible by the first processing device. The method also includes receiving, by the first processing device, an indication that the second relay processing device has transmitted the read command and/or the write command to the I/O device.

Relay mechanism to facilitate processor communication with inaccessible input/output (I/O) device

A module of a distributed process control system has a prior art kernel submodule, a peripheral submodule, and an interface circuit to provide for communications between the two submodules. The kernel submodule communicates with the interface circuit over a module BUS which includes a data BUS and an address BUS. The peripheral submodule communicates with the interface circuit over a peripheral component interface (PCI) BUS, a single thirty two bit BUS which is incompatible with the module BUS. The interface circuit permits such communications between the two submodules without requiring any hardware or software changes to the kernel submodule and the module BUS, nor to components of the peripheral submodule or its PCI BUS. The interface circuit includes interface registers, a control circuit which determines which submodule is permitted to write or read data and/or address into or from a given register of the interface registers. Input circuits controlled by control signals produced by the control circuit determines the source of the data and/or addresses written into a given register. An output circuit under the control of the control circuit determines the BUS over which the contents of a given register are transmitted to the addressed submodule.

Universal operator station module for a distributed process control

A memory unit, made up of a plurality of BY-4 memory devices, has a plurality of computer words, each computer word including a predetermined number of data bits and a predetermined number of check bits. An error detection and correction (EDAC) apparatus interfaces with the memory unit for detecting and correcting a single bit error of the computer word, detecting a two bit error of the computer word, and detecting all two, three, and four bit errors of a single memory device. Matrix logic generates the check bits from preselected participating data bits of the data bits of the computer word being fetched. Compare gate logic compares check bits from the memory unit to corresponding check bits generated by the matrix logic to generate syndrome bits. Detection logic decodes the syndrome bits in accordance with a predetermined matrix mapped to identify one and two bit errors, to identify two, three, and four bit errors of the computer word when such errors are associated with the same BY-4 memory device, and to generate status signals associated with the decoding. Correction gate logic corrects the data bit of the computer word identified as being in error.

Error detection and correction apparatus in a BY-4 RAM Device

A local area network has a plurality of modules, each module having a corresponding timing subsystem. Each timing subsystem includes a clock unit for generating clock pulses, and an a.c. power source. Each timing subsystem is capable of having the timing information generated by each timing subsystem substantially synchronized to the timing information generated by a timing subsystem designated as a master timing subsystem. Each timing subsystem includes a first element, adapted to receive clock pulses and an a.c. reference signal generated from an a.c. power source, which generates timing information from the clock pulses or the a.c. reference signal in response to commands from the module. A register element stores the timing information generated. A second element updates the timing information stored in the register element with timing information included in a timing frame in response to a predetermined command from the module. The timing frame is periodically transmitted by the timing subsystem designated as the master timing subsystem, to each timing subsystem of each module. The timing frame includes timing information generated by the master timing subsystem, thereby resulting in having the timing information of each timing subsystem of each module substantially the same as the timing information of the master timing subsystem.

Apparatus for substantially syncronizing the timing subsystems of the

Method and apparatus for synchronizing to a desired degree of accuracy the timing subsystems of the modules of a distributed local area network by the master and the slave. Each module includes a Module Central Processing Unit (MCPU) and a source of clock signals. Each MCPU includes a digital timing subsystem which produces a fine timing, a synchronization, and a real time timing signal. Two of the timing subsystems are provided with driver circuits one designated as the master and the other as the slave. Each timing subsystem, alternately receives the timing frames transmitted over the two cables of the network by the master and the slave. All timing subsystems other than the master, synchronize with the master. The slave transmits its timing frame in synchronization with the master.

Method and apparatus for synchronizing the timing subsystems of the

A computer system includes at least on error detecting circuit for checking data bits and an associated check bit to verify that the data does not contain an error. An apparatus for verifying the operation of the error detection circuit comprises a generator unit operatively connected to said data lines for receiving data bits, for outputtting a verification signal and a check bit signal. The verification signal indicates the validity of the data bits during a read operation, and the check bit signal is generated during a write operation. A gate element having an input terminal to receive at least one check bit controls at least one input to the generator unit. A first control signal is transmitted to the generator unit thereby causing the check bit signal generated by the generator unit to be valid or invalid in response to the first control signal. Further, the check bit associated with the data is transmitted to the generator unit in response to a second control signal. The second control signal indicates the read operation is in process thereby permitting the generator unit to perform a checking operation independent from the first control signal, thereby permitting verification of the error detection circuit, the checking operation being the verification of the data during the read operation.

Parity integrity check logic

A method of synchronizing a digital timer with the frequency of a source of A.C. power to provide long term temporal stability. The timer produces internal, fine resolution, synchronization and real time timing signals from a source of clock signals. The periods of all the timer produced timing signals are integral multiples of the period of its internal timing signal. A.C. reference timing signals which are a function of the frequency of the source of A.C. power are applied to the timer. The quotient of the period of the synchronization timing signals by that of the A.C. reference timing signals is an integer 'n'. Once n is determined, the number of fine resolution timing signals in each synchronization period for every n.sup.th A.C. timing signal is compared with a reference value. The timing of the fine resolution timing signals is adjusted to maintain the number of fine resolution timing signals in each synchronization period at which the n.sup.th A.C. reference timing signal is produced substantially equal to the reference value.

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Phoenix, AZ, United States of America

David Lyle Kirk