Cypress Semiconductor Corporation

Marvell International Limited

David Luke

Jim Castleberry

David C Gilbert

Dave Gilbert

Frederick Walter Pew

Kris Provencio

Various embodiments provide a USB interface that can operate in either a Host or Device mode using standard Link and/or physical interface circuit (PHY) components which, in at least some embodiments, do not have additional circuitry that is utilized to implement the USB OTG standard.

USB interface configurable for host or device mode

A Universal Serial Bus (USB) device uses a same elasticity buffer for buffering packets for multiple different ports and only necessary packet detection circuitry is associated with the individual ports. A collision detection circuit is further included corresponding with information received from the packet detection circuitry. This simplified universal elasticity buffer architecture reduces the complexity and cost of the USB device.

Simplified universal serial bus (USB) hub architecture

An interface controller includes configuration circuitry generated based on a configuration package associated with endpoint configuration parameters. The configuration circuitry is used for configuring logic circuitry in the interface controller for different endpoint configurations.

Configurable USB interface with virtual register architecture

Hardware Description Language (HDL) code is created for an interface controller so that logic requiring device-specific configuration refers to a parameter file. This set of parameters lets components in a bridge circuit provide support for the same configuration. In another aspect of the invention, a control circuit identifies isochronous endpoints and non-isochronous endpoints. A buffer is configured into a first FIFO mode for isochronous endpoints and configured into a second FIFO mode for non-isochronous endpoints.

Method and apparatus for configuring an interface controller wherein ping pong FIFO segments stores isochronous data and a single circular FIFO stores non-isochronous data

A Universal Serial Bus to parallel bus bridge includes a Universal Serial Bus port that receives a serial bit stream of data and commands in a Universal Serial Bus protocol from a USB host computer. A parallel bus port on the bridge includes parallel port registers and state machines coupled to a peripheral device. A USB controller core is coupled between the Universal Serial Bus port and the parallel bus port and converts data and commands between the Universal Serial Bus protocol and the parallel bus protocol. A sequencer is coupled between the USB controller core and the parallel bus port. A sequence of sequencer commands is loaded into memory in the USB bridge and used by the sequencer to perform a sequence of parallel port operations. The sequencer performs the commands autonomously without intervention from the USB host computer. Because the host computer does not have to initiate a USB transaction for each individual parallel port operation, the sequence of operations is completed in a shorter amount of time.

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Boise, ID, United States of America

David Luke