Freescale Semiconductor,inc.

Sand 9, Inc.

Motorola Corporation

David Locascio

Douglas Alan Garrity

Jan H Kuypers

Reimund Rebel

Brandt Braswell

Andrea Niederkorn

Suhail Agwani

Methods and apparatus for calibration and temperature compensation of oscillators having mechanical resonators are described. The method(s) may involve measuring the frequency of the oscillator at multiple discrete temperatures and adjusting compensation circuitry of the oscillator at the various temperatures. The compensation circuitry may include multiple programmable elements which may independently adjust the frequency behavior of the oscillator at a respective temperature. Thus, adjustment of the frequency behavior of the oscillator at one temperature may not alter the frequency behavior at a second temperature.

Methods and apparatus for calibration and temperature compensation of oscillators having mechanical resonators

Methods and apparatus for tuning devices having resonators are described. Phase shifters are included in the circuits and used to shift the phase of the output signal(s) of the resonators. In some implementations, the phase shifters are configured in a feedback loop with the resonators. One or more of the apparatus described herein may be implemented as part, or all, of a microelectromechanical system (MEMS).

Methods and apparatus for tuning devices having resonators

A converter () adapted to convert an analog input signal into a digital output signal includes an analog input terminal () for receiving the analog input signal, a Redundant Signed Digit (RSD) stage () coupled to the analog input terminal, and a digital section (). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.

Single stage cyclic analog to digital converter with variable resolution

A switched-capacitor gain stage suitable for use with a pipelined analog to digital converter ('ADC') is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase), and the gain stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The gain stage provides equal input loading for the input stages, which enhances the performance of the ADC.

Programmable dual input switched-capacitor gain stage

A pixel signal amplification circuit ( ) receives a signal from a pixel element. A first semiconductor switch ( ) is connected to the pixel element and transfers a reset value of the pixel signal to a first storage capacitor (C ). A second semiconductor switch ( ) is also connected to the pixel element and transfers a sampled pixel signal to a second storage capacitor (C ). A differential voltage amplifier (OP ) generates an amplified signal of the difference between the values stored on the first and second storage capacitors (C and C ).

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Chandler, AZ, United States of America

David Locascio