National Semiconductor Corporation

David Lindsay Broughton

Jeffrey Mark Huard

Kim Yeow Wong

Edson Wayne Porter

Craig M Davis

Wayne Porter

A load sensing buffer circuit for providing a buffered clock signal with controlled switching current noise (di/dt) in which the input clock signal is selectively gated to provide successively generated source and sink current components as part of the buffered output signal, with the timing of such current components being dependent upon load capacitance.

Load sensing buffer circuit with controlled switching current noise (di/dt)

A method for internally resetting a charge pump is provided that includes receiving an up signal and a down signal simultaneously. A feedback signal is generated based on the up and down signals. The feedback signal is provided internally to the charge pump. The charge pump is reset based on the feedback signal.

Method and system for internally resetting a charge pump

A circuit for controlling a phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock includes frequency dividers with selectable divisors for the reference and feedback signals, and a phase detector having a charge pump output circuit with selectable output current ranges. During acquisition of phase lock by the PLL, the divisors for the reference and feedback signal frequency dividers are increased by the same factor, and the charge pump current range is increased by the same ratio. As a result, the reference rate is decreased as the charge pump current range is increased simultaneously by the same ratio. Meanwhile, the linear loop bandwidth and phase margin remain substantially constant.

Control circuit for phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock

A gain control for a phase locked loop circuit is provided. In the phase-locked loop circuit, a voltage controlled oscillator generates a reference signal responsive to the level of a tuning voltage. A phase detector generates the tuning voltage update, which is indicative of a phase relationship between the reference signal and an input signal. A feedback circuit detects the tuning voltage and generates an adjustment signal in response. The adjustment signal is then used to adjust the loop gain at any specific tuning voltage. In a specific example, the adjustment signal is used to adjust the current gain of the phase detector in a manner that is complementary to the non-linear voltage gain of the voltage-controlled oscillator.

Method and circuit for improving lock-time performance for a phase-locked loop

Oscillator control circuitry for a phase lock loop, including phase detection circuitry, control signal generator circuitry, bias control circuitry and charge pump circuitry. The control signal generator circuitry introduces specific and distinct time delays to the phase signals from the phase detection circuitry representing the phase difference between the reference and oscillator output signals. These time delays cause the bias control circuitry to enable and disable the output charge pump circuitry slightly before and after, respectively, those time intervals during which an output source (&ldquo;pump up&rdquo;) or sink (&ldquo;pump down&rdquo;) current is needed to drive the oscillator via the loop filter. This produces charge pump circuitry output signals with significantly faster rise and fall times and shorter pulse widths, thereby resulting in a charge pump output signal with higher SNR and reduced spurious signal energy.

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Tacoma, WA, United States of America

David Lindsay Broughton