Altera Corporation

Intel Corporation

David Lewis

Andy Louie Lee

Vaughn Betz

Bruce B Pedersen

Paul Leventis

Sinan Kaptanoglu

Christopher F Lane

Valavan Manohararajah

David Cashman

Henry Kim

Srinivas T Reddy

Ryan Fung

Richard G Cliff

Michael David Hutton

Cameron R McClintock

James G Schleicher

Brian D Johnson

Gregg William Baeckler

Jeffrey Christopher Chromczak

David Galloway

Richard Yuan

Rahul Saini

Herman Henry Schmit

Tim Michael Vanderhoek

Chris Lane

Mike Hutton

Hyun Mo Yi

Ketan H Zaveri

Chris Wysocki

Michael Chan

Alexander Marquardt

Thomas Yau-Tsun Wong

Vikram Santurkar

Jinyong Yuan

Mark Bourgeault

Ketan Padalia

Martin Langhammer

Irfan Rahim

Philip Pan

Peter John McElheny

Volker Mauer

Ninh D Ngo

Henry Y Lui

Keone Streicher

Carl Ebeling

Yi-Wen Lin

Yow-Juang W Liu

Suleyman Sirri Demirsoy

Wai-Bor Leung

Jay Schleicher

Jeffrey T Watt

David Edward Jefferson

Srinivas Perisetty

Triet M Nguyen

Paul B Ekas

Ajay K Ravi

Sarathy Sribhashyam

Kostas Pagiamtzis

Timothy Vanderhoek

Joseph Huang

Tony K Ngai

Dana How

Yanzhong Xu

Haiming Yu

David Neto

James G Schleicher, Ii

Giles V Powell

Lu Zhou

Bruce B Pederson

Jeffrey Chromczak

Hao-Yuan Howard Chou

Zahir Parpia

Ray Ruey-Hsien Hu

Robert Blake

Tim Vanderhoek

A programmable integrated circuit device includes a plurality of clusters of programmable logic resources. Programmable device interconnect resources allow user-defined interconnection between the clusters of programmable logic resources. A plurality of specialized processing blocks have dedicated arithmetic operators and programmable internal interconnect resources, and having inputs and outputs programmably connectable to the programmable device interconnect resources. A plurality of embedded memory modules have inputs and outputs programmably connectable to the programmable device interconnect resources. Instruction sequencing circuitry is provided, and the instruction sequencing circuitry, at least one of the specialized processing blocks and at least one of the embedded memory modules, are programmably connectable to form a processor, where the memory module serves as instruction memory. Optionally, a dedicated instruction bus communicates the instructions from the embedded memory module or modules to the specialized processing block or blocks.

Configuring programmable integrated circuit device resources as processors

A method for designing a system on a target device includes placing the system on the target device. Timing analysis is performed on the placed system to model delays by using a plurality of localized functions that overlap.

Method and apparatus for performing symbolic timing analysis with spatial variation

An integrated circuit include multiple regions, wherein at least one region includes a control circuit. The control circuit receives a target voltage value to supply to the region that enables the region to operate at a target speed. The control circuit also receives a first criticality value of a first path of a design programmed in the region. The first criticality value is based on a first propagation time of the first path and a first allowable time to traverse the first path while enabling the region to operate at the target speed. The control circuit further instructs a power regulator to supply voltage to the region based at least in part on the target voltage value and the first criticality value. The integrated circuit also includes the power regulator communicatively coupled to the at least one region. The power regulator supplies power to the at least one region.

Regional design-dependent voltage control and clocking

Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.

Omnibus logic element

An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant.

Pipelined interconnect circuitry with double data rate interconnections

A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements.

Integrated circuit device configuration methods adapted to account for retiming

Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits ('IC') that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of resistive switches to be programmed. In other embodiments, methods are provided for programming resistive switches without violating given power constraints. These and other embodiments are described further herein.

Routing and programming for resistive switch arrays

An integrated circuit with programmable logic is provided. The programmable logic may include multiplexers that are actively used by a custom logic design or unused. To ensure that these multiplexers do not suffer from aging effects when they are not in use, the multiplexers may be provided with aging prevention circuitry. In particular, such a multiplexer may include an input selection stage that is coupled in series with a tristate buffer stage. The input selection stage may include pass transistors or full CMOS transmission gates. The tristate buffer stage may include at least two pairs of output driving transistors, with gates that are selectively shorted when the multiplexer is activated using additional transmission gate circuits. The aging prevention circuitry may include tie-off transistors that are activated to drive the gate-to-source voltages of the output driving transistors to zero volts whenever the multiplexer is not in use.

Tristate multiplexers with immunity to aging effects

An integrated circuit includes rows of circuits. A first region of the integrated circuit includes a first portion of each of the rows of circuits, and a second region of the integrated circuit includes a second portion of each of the rows of circuits. The integrated circuit shifts functions for a first subset of the rows of circuits to a second subset of the rows of circuits in the first region based on a first defect in a first one of the rows of circuits in the first region. The integrated circuit shifts functions for a third subset of the rows of circuits to a fourth subset of the rows of circuits in the second region based on a second defect in a second one of the rows of circuits in the second region.

Techniques for bypassing defects in rows of circuits

An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, an arithmetic circuit, and a control circuit. The control circuit may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement first-in first-out modules, shift registers, or delay-line modules in addition to implementing memory modules with random access.

Configurable storage blocks with embedded first-in first-out and delay line circuitry

Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

Circuitry for implementing multi-mode redundancy and arithmetic functions

An integrated circuit (IC) includes a metastability-hardened synchronization circuit. The metastability-hardened synchronization circuit includes a plurality of sampling circuits, and a multiplexer. The sampling circuits sample an input signal to generate a plurality of sampled signals. The multiplexer generates an output signal from the plurality of sampled signals.

Metastability-hardened synchronization circuit

Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions include register circuitry that may be controlled by register control signals. A clock enable feedback loop circuit controlled by a clock enable control signal may couple the register output to the register input. The clock enable feedback loop circuit may facilitate adjustment of register locations within a design while ensuring correct clock enable functionality. A group of programmable logic regions may have shared input selection circuitry that selects register control signals and produces delayed versions of the signals that are shared by the group. If desired, each programmable logic region may be provided with adjustable delay circuitry that individually adjusts control signal delay for registers of that programmable logic region.

Integrated circuits with improved register circuitry

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David Lewis