Google Inc.

David Levinthal

Benjamin Charles Serebrin

Kevin D Kissell

Clinton Wills Smullen, Iv

A method of managing processor caches. The method includes invalidating a cache line from a first instruction cache level and in response to invalidating the cache line from the first cache level, fetching data associated with the invalidated cache line from a third cache level or memory and writing the fetched data to a second cache level. The third cache level is larger or differently associative than the second cache level and the second cache level is larger or differently associative than the first cache level.

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Los Gatos, CA, United States of America

David Levinthal