Texas Instruments Corporation

David Leonard Larkin

Dhaval Atul Saraiya

Byron Lovell Williams

Ashish V Gokhale

Thomas Dyer Bonifield

Jeffrey Alan West

Weidong Tian

Lily Springer

Shrinivasan Jaganathan

Makoto Takemura

Ricky Dale Jordanger

Quang X Mai

David Wayne Stout

George Ernest Harris

William David Smith

A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A first dielectric layer has a first dielectric constant located over a semiconductor substrate. A metal structure located over the first dielectric layer has a side surface. A second dielectric layer having a second different dielectric constant is located adjacent the metal structure. A dielectric structure located between the side surface of the metal structure and the second dielectric layer has the first dielectric constant.

Structure and method for improving high voltage breakdown reliability of a microelectronic device

A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A metal plate having a top surface and a side surface is located over a first dielectric layer. A second dielectric layer of a second different material is located over the first metal plate. A dielectric structure of the first material is located over the side surface of the metal plate and over the surface of the first dielectric layer.

A method and structure for improving high voltage breakdown reliability of a microelectronic device, e.g., a galvanic digital isolator, involves providing an abatement structure around metal plate corners of a high voltage isolation capacitor to ameliorate the effects of an electric field formed thereat during operation of the device due to dielectric discontinuity.

An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

High voltage polymer dielectric capacitor isolation device

The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate () located over or in a semiconductor substrate (), and an insulator () located over the first capacitor plate (), at least a portion of the insulator () comprising an interlevel dielectric layer (, or). The integrated high voltage capacitor further includes capacitance uniformity structures () located at least partially within the insulator () and a second capacitor plate () located over the insulator ().

Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor

Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal.

Systems and methods of digital isolation with AC/DC channel merging

The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate () located over or in a substrate (), and an insulator () located over the first capacitor plate (), at least a portion of the insulator () comprising an interlevel dielectric layer (or). The integrated high voltage capacitor further includes a second capacitor plate () located over the insulator () and a top-level dielectric layer () located at least partially along a sidewall of the second capacitor plate ().

Integrated high voltage capacitor having a top-level dielectric layer and a method of manufacture therefor

A method for decreasing CHC degradation is provided. The method includes providing a semiconductor device ( ) having at least one metal layer ( ) completed. Then, a planarizing dielectric layer ( ) is added to the semiconductor device ( ). The semiconductor device ( ) is heated in a hydrogen rich environment until hydrogen completely saturates the semiconductor device ( ).

Method for decreasing CHC degradation

A patternless, self-aligning method of forming a floating gate on a silicon wafer having a plurality of raised field oxide isolation structures. The method of the present invention includes depositing a polysilicon layer onto the silicon wafer and the raised field oxide isolation structures, depositing a polysilicon etch masking layer onto the polysilicon layer, and planarizing the polysilicon etch masking layer. The polysilicon etch masking layer is then etched to expose the polysilicon layer over the raised field oxide isolation structures. The exposed polysilicon layer is then etched to remove the polysilicon layer over the raised field oxide isolation structures. The remaining polysilicon etch masking layer is then removed, leaving a plurality of polysilicon regions covering the silicon wafer between the field oxide isolation structures.

Growing community of inventors

Richardson, TX, United States of America

David Leonard Larkin