Silicon Graphics, Incorporated

David Leo McCall

David Edward McCracken

Martin M Deneroff

Kenneth M Sarocky

A configurable synchronizer (,) for DDR-SDRAM (,) is provided that includes a strobe select module (,) operable to receive a memory select signal (,) and to pass strobe signals (,) from one or more DDR-SDRAMs (,) to a number of synchronizer circuits (,) corresponding to data signals (,) passed in parallel by each DDR-SDRAM as indicated by the memory select signal (,). A rising edge latch (,) receives a rising edge data signal (,) and latches the rising edge data signal (,) through the rising edge latch (,) on a rising edge of the strobe signal (,). A falling edge latch (,) receives a falling edge data signal (,) and latches the falling edge data signal (,) through the falling edge latch (,) on a falling edge of the strobe signal (,). A data signal selector (,) receives a data order control signal (,) and forwards the rising edge data signal (,) from the rising edge latch (,) to an intermediate output (,) on either a rising edge of a memory clock cycle (,) or a falling edge of a memory clock cycle (,) followed by forwarding the falling edge data signal (,) from the falling edge latch (,) to the intermediate output (,) on an opposite edge of the memory clock cycle (,) in response to the data order control signal (,). An output latch (,) receives the intermediate output (,) and latches the intermediate output (,) through the output latch (,) to an output signal (,) on each core clock cycle (,).

Configurable synchronizer for double data rate synchronous dynamic random access memory

A memory system that includes switches for controlling data transfer that are disposed on the motherboard. The switches are selectively coupled to a controller and to connector receptacles that are adapted to receive a memory module. The memory system also includes resistors that are disposed on the motherboard for terminating data signals. In one embodiment, memory modules are accessed in pairs. That is, the data switches are used to control the flow of data signals such that data signals only flow to one pair of memory modules at any particular time. In one embodiment, the memory system of the present invention includes eight memory modules that use DDR SDRAM memory components. When 8 Mbit, 16 Mbit, 32 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 128 megabytes (Mbytes) to 1 gigabyte (Gbyte).

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Eauclaire, WI, United States of America

David Leo McCall