United Microelectronics Corp.

David Lee

Water Lur

Kuang-Chih Wang

Ming-Sheng Yang

Chewnpu Jou

Cheng-Wang Huang

An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus minimizing fringing fields between the lines. Multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels.

Air gap for dual damascene applications

An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with either damascene or conventional integrated circuit metallization schemes. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

Air gap formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device

An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

Air gap for tungsten/aluminum plug applications

A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co&#x2014;Ti&#x2014;along with layers of Co&#x2014;are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.

Wafer processing apparatus and methods for depositing cobalt silicide

Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device

An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request from at least one of the slave chips, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion, with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer.

Apparatus and method for serial data communication between plurality of chips in a chip set

A semiconductor device that includes cobalt-silicide based contacts is disclosed, as well as a process for making the same. Combinations of alloyed layers of Co&#x2014;Ti&#x2014; along with layers of Co&#x2014; are arranged and heat treated so as to effectuate a silicide reaction on a silicon substrate. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor devices and processes.

Semiconductor device with cobalt silicide contacts and method of making the same

A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co&mdash;Ti&mdash; along with layers of Co&mdash; are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.

Method and system for making cobalt silicide

A method of fabricating a MOS capacitor in a complementary MOS fabrication process with dual-doped poly gates comprises providing a substrate of a first conductive type, the substrate having a first well of the first conductive type and a second well of a second conductive type. A dielectric layer is formed on the substrate. A first poly gate of the first conductive type is formed on the dielectric layer over the first well and a second poly gate of the second conductive type is formed on the dielectric layer over the second well. A first doped region of the first conductive type is formed in the substrate at each side of the first poly gate. A second doped region of the second conductive type is formed in the substrate at each side of the second poly gate layer. A spacer is formed on sidewalls of the first poly gate and the second poly gate, wherein a portion of the dielectric layer is also removed to expose a portion of the first doped region and a portion of the second doped region. An implantation is performed on the exposed portion of the first doped region with dopants of the first conductive type, so as to form a first substrate electrode. An implantation process is performed on the exposed portion of the second doped region with dopants of the second conductive type to form a second substrate electrode.

Method of fabricating a MOS capacitor

An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request from at least one of the slave chips, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion. with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer.

A method of forming a metal via on a semiconductor substrate having a metal layer and a dielectric layer on the metal layer, which uses an intermediate mask layer as a mask in forming the metal via instead of using a photoresist as a mask. Therefore, the spin-on glass (SOG) layer in the dielectric layer is not exposed to plasma or solvent, thereby preventing the formation of polymers which cause poor step coverage and sometimes even contact failure in the metal via.

Method for forming metal via

A method of manufacturing a twin-tub structure for a CMOS (Complementary Metal Oxide Semicondcuctor) device is described. A first conductivity-imparting dopant is implanted in a silicon substrate. A photoresist layer is formed over a portion of the silicon substrate, to act as a mask. A portion of the top surface of the silicon substrate is removed in the region not masked by the photoresist layer. A second conductivity-imparting dopant, of an opposite type to the first conductivity-imparting dopant, is implanted into the region of the silicon substrate not masked by the photoresist layer. The photoresist layer is removed. A first insulating layer is formed over the silicon substrate. A second insulating layer is formed over the first insulating layer. The second insulating layer is patterned to form an active region mask centrally located over the planned location of each tub of the twin tub structure. Tubs are formed in the silicon substrate. Field oxide regions are formed in and on the surface of the silicon substrate, between the active region masks. The remainder of the second insulating layer is removed. A third conductivity-imparting dopant, of the same type as the second conductivity-imparting dopant, is implanted into the same region as the second conductivity-imparting dopant.

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Hsinchu, Taiwan

David Lee