Altasens, Inc.

Rockwell International Corporation

Pictos Technologies, Inc.

Biomorphic Vlsi, Inc.

Other

Ess Technology, Inc.

David Lawrence Standley

Lester Joseph Kozlowski

Laurent Blanquart

Craig Charles Reinhart

Gaurang Patel

Mihail M Milkov

Amit Mittra

Joey Shah

H Taichi Wang

Bimal P Mathur

Ying Huang

Shih-Chii Liu

Manjunath S Bhat

Aspects describe front-end pixel fixed pattern noise correction in imaging arrays having wide dynamic range. A photosensor of a first pixel in a first row of an array is reset and a first reset level of the first pixel is measured. The array comprises a plurality of pixels arranged in rows and columns. In response to a result of the first reset level, a reset bus is altered. A feed-forward adjustment of the photosensor of the first pixel is performed to substantially remove fixed-pattern noise. An external readout from the photosensor can occur with substantially all the fixed-pattern noise removed. In some aspects, the adjustment is performed by a switched capacitor block.

Front-end pixel fixed pattern noise correction in imaging arrays having wide dynamic range

Various technologies described herein pertain to automatically adjusting the strength of a voltage booster of an image sensor. A self-scaled voltage booster includes a regulator, a controller, and two or more charge pumps that can be selectively enabled and disabled by the controller. The controller generates controller signals for the charge pumps based on a duty cycle of a regulator signal generated by the regulator. Moreover, the controller can maintain the controller signals without modification for at least a predetermined minimum period of time after a prior modification of at least one of the controller signals. Further, the controller can include a duty cycle and delay module (or a plurality of duty cycle and delay modules) that detects the duty cycle of the regulator signal and maintains the controller signals without modification for at least the predetermined minimum period of time.

Self-scaled voltage booster

Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements.

Low power slope-based analog-to-digital converter

An operational trans-conductance amplifier circuit having a voltage clamp circuit. The clamp circuit utilizes low area and power overhead, has a sharp clamp characteristic, and little degradation in the small-signal DC gain at the 'knee' of the clamp characteristic. The clamp circuit includes a comparator circuit and a current control circuit. The amplifier and clamp circuits may further include a clamp voltage generator circuit.

Operational trans-conductance amplifier with output clamp circuit

A system and method for averaging incident light on plural pixels using a CMOS sensor is provided. The process includes resetting all pixels in a given region during a reset phase; and reading a voltage of a floating reset node as a function of time during a measurement phase. During the reset phase, an access select signal and a reset voltage are both high. The measurement phase begins when the access select signal is low and the reset voltage is still high. The system and method may be used to perform automatic exposure control and automatic white balancing operations.

System and method for automatic exposure control and white balancing for CMOS sensors

A method and system for inter-processor communication in a pixel array in a CMOS sensor is provided. The system includes a bus for transmitting information between a first processor and a second processor, wherein such information is used for performing image processing operations in the pixel array in an analog domain. The bus may be a pixel read-out bus and/or an access bus. The information is used to perform outlier detection, bad pixel detection, and/or bad pixel correction in the analog domain, or any other image processing operation. The method includes sharing information between a first and a second processor; and using the information to perform image processing operations in an analog domain.

Method and system for pixel bus signaling in CMOS image sensors

A method and system for automatic bad pixel correction in image sensors is provided. The process includes identifying outlier pixels, identifying bad pixels, and performing bad pixel correction. Bad pixels are identified by comparing pixels in a single row or more than one row. A bad pixel value is replaced by a pixel value that depends on the pixel value of non-bad pixels located next to the bad pixel. The system includes means for identifying outlier pixels, means for identifying bad pixels, and means for performing bad pixel correction.

Automatic bad pixel correction in image sensors

An active-pixel low-noise imaging system for implementation in CMOS or in other semiconductor fabrication technologies uses three transistors and a single capacitance per pixel. The first transistor serves as a reset and a transimpedance amplifier to facilitate high impedance and suppress reset noise without requiring expensive on-chip or off-chip memory. The second transistor is an access MOSFET used to read the signal from each pixel and multiplex the signal outputs from an array of pixels. The third MOSFET resets the detector after the integrated signal has been read. Since the detector sense node is &ldquo;pinned&rdquo; by the feedback amplifier, reset noise is reduced to that generated by the much smaller feedback capacitance. In addition, by using a small but well-defined feedback capacitor, an amplifier with a narrow bandwidth can be used, provided its unity-gain frequency is sufficient. Since the pixel-base amplifier's output capacitance is far smaller than the bus capacitance, the total energy consumed during reset is very small and overall power consumption is kept at a level consistent with battery-powered operation.

Low-noise CMOS active pixel sensor for imaging arrays with high speed global or row reset

An imaging array of active pixel sensors uses a compact three transistor CMOS implementation for each pixel. A current source at the top of each column creates a distributed feedback amplifier for each pixel in a selected row. The reset amplifier acts as a variable resistance in the source-follower amplifier feedback circuit. The variable resistance is controlled by a range reset voltage applied to the reset amplifier thereby nulling the photodiode reset noise.

Compact low-noise active pixel sensor with progressive row reset

An active pixel sensor circuit including a photodetector, a first MOS transistor functioning as the driver of a source follower amplifier during signal readout, a second MOS transistor serving as a pixel readout transistor, a third MOS transistor serving as a photodetector reset transistor, and a reset noise cancellation circuit including a fourth MOS transistor, first and second capacitances, and an amplifier having a gain which is a specified multiple of the ratio of the first to the second capacitance. The first capacitance is connected in parallel to the photodector. The amplifier reduces the reset noise caused by resetting the photodector without having to implement correlated double sampling.

Low-noise active-pixel sensor for imaging arrays with high speed row reset

An imager pixel including a photodetector, a first MOS transistor functioning as the driver of a source follower amplifier, a second MOS transistor functioning as a pixel readout transistor, and a third transistor performing a dual function to reset the photodetector during a first time interval and cancel reset noise by serving as a weak current source during a second time interval.

Active pixel sensor with capacitorless correlated double sampling

An imager pixel including a photodetector, a first MOS transistor functioning as the driver of a source follower amplifier during signal readout, a second MOS transistor serving as a pixel readout transistor, a third MOS transistor serving as a photodetector reset transistor, and a reset noise cancellation circuit including a fourth MOS transistor, first and second capacitances, and an amplifier having a gain which is the inverse of the ratio of the first to the second capacitance.

An imaging array of active pixel sensors uses a reset amplifier in each pixel in a four transistor CMOS implementation. The reset amplifier acts as a variable resistance in the source-follower amplifier feedback circuit. The variable resistance is controlled by a range reset voltage applied to the reset amplifier thereby nulling the photodiode reset noise. The ramp reset voltage is applied to all reset amplifiers of all pixels at the same time, thereby providing for reset of the entire array at the same time, i.e., global reset.

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David Lawrence Standley