Agilent Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies Enterprise IP (singapore) Pte. Ltd.

Avago Technologies General IP Pte, Ltd.

David Lawrence Linam

Guy Harlan Humphrey

Scott T Evans

Christopher George Helt

Jeffrey R Rearick

Gayvin E Stong

Barbara Jean Duffner

Richard Alan Krzyzkowski

Benjamin P Haugestuen

Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison.

Continuous tuning of preamble release timing in a double data-rate memory device interface

A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined by the write-leveling procedure. The determination can then be used to ensure that the data strobe signals of all source synchronous groups are aligned with the same edge of the clock signal.

Write level training using dual frequencies in a double data-rate memory device interface

Circuits and methods for reducing noise in the power supply of circuits coupled to a bidirectional bus are presented. The circuits and methods are responsive to an idle condition on the bidirectional bus. The control signal is applied to and changes an electrical characteristic within the receiver to generate a voltage offset. The voltage offset prevents unintended voltage transitions in the power supply of circuits coupled to the bidirectional bus from generating a signal transition on an output signal connection of the receiver.

Circuits and methods for reducing noise in the power supply of circuits coupled to a bidirectional bus

An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.

Interfaces, circuits, and methods for communicating with a double data rate memory device

A method and apparatus for testing an integrated circuit interconnect comprises an IC having circuitry embedded in the IC capable of providing a pseudo time domain reflectometry test by launching a test transition onto the interconnect and capturing a reflection of the test transition.

Method and apparatus for an embedded time domain reflectometry test

A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each programmably electrically connectable according to the hybrid binary/thermometer code in parallel between a voltage source and the signal pad. The plurality of impedance legs are partitioned into one or more set pairs of binary stepped impedance legs and corresponding thermometer stepped impedance legs. A binary set of calibration signals in the hybrid binary/thermometer code steps a given set of binary stepped impedance legs according to a binary code and a thermometer set of calibration signals in the hybrid binary/thermometer code steps the corresponding set of thermometer stepped impedance legs according to a thermometer code once per full count iteration of the binary set of calibration signals.

Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers

A differential register slave structure is presented. In one embodiment, a differential register includes a storage node (). The storage node () stores and holds the differential values generated by the differential register. In one embodiment of the present invention, on power-up, when the state of various clocks (i.e., master, slave) in the differential register may be indeterminate, the storage node () will discharge the differential values and the differential register will produce a differential output.

Differential register slave structure

A novel output driver for an integrated circuit, and method for controlling the slew rate of output signals driven by the output driver, is presented. The output driver employs a delayed activation of a succession of weak impedance zip legs followed by a preferably delayed activation of a succession of strong impedance drive legs. During a transition of an output signal on an output node of the driver from a first drive state to a second drive state, each zip leg, in its turn, turns off driving the output node to the first drive state and then turns on driving the output node to the second drive state. Once all zip legs have been activated, the activation of the succession of strong drive legs supplements the combined current provided by the zip legs to provide the full required drive current of the driver driving the output node to the second drive state.

Tristateable CMOS driver with controlled slew rate for integrated circuit I/O pads

An electronic circuit for enabling differential tests. In representative embodiments, the electronic circuit includes a first differential receiver having first and second inputs and an output, a first switch having first and second data inputs, a control input, and an output, and a first control device having an output. The first input of the first differential receiver is connected to a first contact and to a first single ended receiver input, and the second input of the first differential receiver is connected to a second contact and to a second single ended receiver input. The first data input of first switch is connected to first single ended receiver output, and the second data input of first switch is connected to first differential receiver output. The first control device output is connected to first switch control input. When first control device output is in a specified condition, first data input of first switch is connected to first switch output, otherwise second data input of first switch is connected to first switch output.

Differential self-test of input/output circuits

An apparatus and method permits quick response to a transition at an input port and subsequent propagation of the transition to the output port while being able to process a wide variety of input signal properties. A receiver apparatus comprises at least first and second receivers, each receiver accepting an input signal and tuned for optimal response to a set of known input signal properties. Either first and second primary transition propagation elements or secondary transition propagation element propagates a first transition from one of the receivers. A universal transition propagation element propagates the first transition to an output. A pass gate receives a signal based upon the output and inhibits transmission of the signal based upon the output until the first and second intermediate signals are equivalent whereupon the pass gate is placed in low impedance state permitting the signal based upon the output to be held in a storage node as the preset signal.

Receiver apparatus and method of propagating a signal

Insertion delay associated with receiving and distributing a clock within an IC is removed using a DLL. The structure of a differential receiver in the feedback circuit of the DLL is substantially matched to the structure of an input differential receiver which receives and inputs a differential input clock into the DLL. In this manner, the insertion delay associated with the input differential receiver is removed from a delay-corrected clock output from the DLL. By substantially matching one or more aspects of the feedback circuit to one or more aspects of a clock distribution circuit for distributing the delay-corrected clock, the insertion delay associated with the clock distribution circuit can also be removed from the delay-corrected clock.

Growing community of inventors

Ft. Collins, CO, United States of America

David Lawrence Linam