Intel Corporation

Other

David Lawrence Hill

Derek T Bachand

Chinna B Prudvi

Robert J Greiner

Paul D Breuder

Stephen S Pawlowski

Gurbir Singh

Donald D Parker

Deborah T Marr

Matthew A Fisch

James B Crossland

Dion Rodgers

David A Koufaty

Frank Binns

Shiv Kaushik

David I Poisner

Tim Frodsham

Anant S Deval

Raymond Scott Tetrick

Herbert H J Hum

Keshavan K Tiruvallur

Mark R Waggoner

Chlnna B Prudvi

In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.

Communicating via an in-die interconnect

Architectures and techniques that allow legacy pin functionality to be replaced with a 'virtual wire' that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.

Virtualization of pin functionality in a point-to-point interface

A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.

Prioritized bus request scheduling mechanism for processing devices

Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.

Method and apparatus for suspending execution of a thread until a specified memory access occurs

A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.

Dynamic priority external transaction system

Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having an operand indicating a monitor address and a bus controller. In one embodiment, the bus controller is to assert a preventative signal in response to receiving a memory access attempting to gain sufficient ownership of a cache line associated with said monitor address to allow modification of said cache line without generation of another transaction indicative of the modification. In another embodiment, the bus controller is to generate a bus cycle in response to the instruction to eliminate any ownership of the cache line by another processor that would allow a modification of the cache line without generation of another memory access indicative of the modification.

Coherency techniques for suspending execution of a thread until a specified memory access occurs

Methods, apparatuses, and systems are provided to determine a bootstrap processor. In an embodiment, the method determines a bootstrap processor from a plurality of operable processors in a fault tolerant multiprocessor system irrespective of an initialization time of a particular operable processor.

Method and system to determine the bootstrap processor from a plurality of operable processors

A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.

Enhanced highly pipelined bus architecture

A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a set of snoop status interfaces, an address strobe signal interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic capable of sensing or asserting one or more of a set of snoop status signals for transaction N on the snoop status interfaces during a snoop phase to start in a bus cycle upon the later of three or more bus clock cycles of the bus clock signal after a beginning of a bus cycle of an the assertion of an address strobe signal for transaction N or two or more bus clock cycles of the bus clock signal after a beginning of a bus cycle in which a most recent snoop phase begins.

Snoop phase in a highly pipelined bus architecture

A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.

Quad pumped bus architecture and protocol

A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N- and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N- and deasserts the data busy signal.

Response and data phases in a highly pipelined bus architecture

A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.

Prefetch queue

Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.

Growing community of inventors

Cornelius, OR, United States of America

David Lawrence Hill