O-in Design Automation, Inc.

Other

Mentor Graphics Corporation

David Lansing Dill

Chian-Min Richard Ho

Ping Fai Yeung

Kalyana C Mulam

Tai An Ly

Jing Chyuarn Lin

Lawrence Curtis Widdoes, Jr

Jean-Charles Giomi

Paul Andrew Wilcox

Robert Kristianto Mardjuki

Paul Ii Estrada

Paul Estrada, Ii

Paul Il Estrada

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Method for automatically searching for functional defects in a description of a circuit

A programmed computer generates descriptions of circuits (called 'checkers') that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

Method for automatically generating checkers for finding functional defects in a description of circuit

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

A programmed computer generates descriptions of circuits (called &ldquo;checkers&rdquo;) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

Method for automatically generating checkers for finding functional defects in a description of a circuit

A programmed computer generates descriptions of circuits (called &ldquo;checkers&rdquo;) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

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Redwood City, CA, United States of America

David Lansing Dill