Oracle International Corporation

Sun Microsystems, Inc.

David L Weaver

John Robert Rose

Darryl J Gove

Robert T Golla

Shasank Kisan Chavan

Jeffrey S Brooks

Gerald Zuraski

Albert Danysh

Prateek Agrawal

Andrew Ewoldt

A system includes a processor and memory including one or more memory region groups, each including a plurality of distinct memory regions. In embodiments, each memory region of a particular memory region group has a same set of memory attributes and is associated with a same attribute group identifier (AGI). In response to an access request to a memory location of a memory region within the particular memory region group, the AGI may be used to identify the set of memory attributes to be applied when executing the access request. In response to a request to change one or more memory attributes of the particular memory region group, update of a single entry changes the memory attributes for all memory regions of the particular memory region group, without accessing individual metadata of each memory region. The update can be accomplished atomically and substantially simultaneously.

Method and apparatus for storing memory attributes

Approaches are described to improve database performance by implementing a RLE decompression function at a low level within a general-purpose processor or an external block. Specifically, embodiments of a hardware implementation of an instruction for RLE decompression are disclosed. The described approaches improve performance by supporting the RLE decompression function within a processor and/or external block. Specifically, a RLE decompression hardware implementation is disclosed that produces a 64-bit RLE decompression result, with an example embodiment performing the task in two pipelined execution stages with a throughput of one per cycle. According to embodiments, hardware organization of narrow-width shifters operating in parallel, controlled by computed shift counts, is used to perform the decompression. Because of the decreased time required to perform RLE decompression according to embodiments, the performance of tasks that use embodiments described herein for decompression of run-length encoded data is made more efficient.

Run-length encoding decompression

A processor having a streaming unit is disclosed. In one embodiment, a processor includes a streaming unit configured to load one or more input data streams from a memory coupled to the processor. The streaming unit includes an internal network having a plurality of queues configured to store streams of data. The streaming unit further includes a plurality of operations circuits configured to perform operations on the streams of data. The streaming unit is software programmable to operatively couple two or more of the plurality of operations circuits together via one or more of the plurality of queues. The operations circuits may perform operations on multiple streams of data, resulting in corresponding output streams of data.

Flexible configuration hardware streaming unit

A processor having a streaming unit is disclosed. In one embodiment, a processor includes one or more execution units configured to execute instructions of a processor instruction set. The processor further includes a streaming unit configured to execute a first instruction of the processor instruction set, wherein executing the first instruction comprises the streaming unit loading a first data stream from a memory of a computer system responsive to execution of a first instruction. The first data stream comprises a plurality of data elements. The first instruction includes a first argument indicating a starting address of the first stream, a second argument indicating a stride between the data elements, and a third argument indicative of an ending address of the stream. The streaming unit is configured to output a second data stream corresponding to the first data stream.

Hardware streaming unit

Virtual registers are mapped to architectural or physical registers according to a register map that is configurable with software. In one embodiment, only privileged software can configure the register map. In another embodiment, a portion of the register map is configurable with non-privileged software, and another portion is only configurable with privileged software. In yet another embodiment the register map is fully configurable by user software. The configurable register map provides backwards compatibility to code written for hardware-defined register mapping, while allowing flexible approaches to register mapping in code generated for a processor architecture using a software controllable register map.

Growing community of inventors

Emerald Hills, CA, United States of America

David L Weaver