Inmos Limited

Stmicroelectronics Gmbh

David L Waller

Michael David May

Jonathan Edwards

A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Microcomputer with high density RAM on single chip

A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Microcomputer with high density RAM in separate isolation well on single

Microcomputer with high density ram in separate isolation well on single

A microcomputer includes an on-chip processor with at least 1K bytes of high density RAM on-chip together with isolation regions to protect the RAM from noise from transistors on-chip operating independently of the RAM.

A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks or microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

A programmable, high speed, single chip microcomputer includes 4K of RAM, ROM, registers and an ALU. Program can be stored in the on-chip RAM. The first local variable of each process to be executed is a workspace pointer (WPTR), and each process has a respective workspace identified by its WPTR. For each process, addressing of other variables is relative to the current WPTR, which is stored in a workpiece pointer register (WPTR REG). Instructions are constant bit size, having a function portion and a data portion loaded, respectively, into an instruction buffer (IB) and an operand register (OREGTR). Memory address locations are formed by combining the contents of the workspace pointer register and the operand register, or the contents of the A Register and the operand register. A set of 'direct functions' obtains data from OREG. 'Indirect functions' use the OREG contents to identify other functions, obtaining data from registers other than the operand register. A 'prefixing' function (PFIX) develops operands having long bit lengths. Scheduling and descheduling of processes are achieved by forming a linked list within the several workspaces for the active processes. Each workspace identifies the workspace pointer of the next process to be executed. Each workspace contains in memory the identification of the next instruction to be executed for that respective process. A 'last pointer' register (LPTR REG.) cooperates in the scheduling operations. Each microcomputer chip can be coupled serially to other such chips on a respective pair of only two wires, each a unidirectional channel. Each channel also has two registers, one for process identification and one for data. Communications are synchronized.

High density ROM in separate isolation well on single with chip

The columns of a memory array are accessed by a plurality of column decoders, each decoder selectively accessing one column in a respective group of columns. Each column decoder can be connected to a respective data line by way of a first transistor, and the data line can also be connected to the decoder of a preceding group of columns by way of a second transistor. The second transistor associated with the first stage can connect the first data line to a spare column decoder accessing a spare group of columns. The conditon of each pair of first and second transistors is controlled by way of a respective normally closed fuse, and generally each column decoder is connected by its first transistor only to its respective data line. However, if defects are found in a group of columns, the associated fuse is blown to isolate that group from its data line. The second transistor is then rendered conductive to connect the data line to the preceding column decoder. Similarly, the data line of each preceding group is connected to the preceding column decoder with the first data line being connected to the spare column decoder.

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Kent, United Kingdom

David L Waller