Harris Corporation

Other

Mostek Corporation

Harris Semiconductor Corporation

David L Taylor

Stephen A Harris

Francisco J Martinez

Terrell M Keene

Eugene E Haggard

Richard N Hartley

Edgar J Flemming

Wiley C Calhoun

Ching-Lin Jiang

Vernon G McKenny

Wayne M Lucas

John A Correa

Rudy A Lopez

Harry E Sullivan

Arvil B Mason

A preamp/driver circuit (18) is disclosed which is operable to interface a Bit Line (14) with a Data Line (20). The Bit Line (14) has a plurality of memory cells associated therewith which are selectable by Word Lines. The preamp/driver (18) decouples the Bit Line (14) from the Data Line (20) and drives Data Line (20) from a separate source. The preamp/driver (18) is comprised of a depletion transistor (22) that has the gate thereof connected to the Bit Line (14) and drives a source follower (26). The source follower (26) drives the Data Line (20) from the supply potential. The system is operable during a restore operation to write back to the Bit Line (14) from the Data Line (20) through a Write transistor (28). The restore operation is effected with a restore amplifier with the Read operation effected through a separate sensing device that converts the voltage on the Data Lines to full logic potentials.

Dynamic random access memory with bit line preamp/driver

An element removal tool for use with transmission lines for fluids (such as natural gas) under pressure which permits replacement of the element, in a specific case the axle box which is coupled between a metering chamber and the indexing mechanism in a gas meter, in a fluid transmission system, without shutting off downstream-customer service, the problem of properly seating the axle box in the undergear which drives it, despite slow rotation of the driving mechanism in the metering chamber, being overcome by dual concentric shafts relatively rotatable and slidable with respect to each other, the inner shaft carrying a socket which engages, firmly, the rotatable indexing shaft of the axle box, the outer shaft carrying a socket which is adapted to firmly engage the flange of the axle box for removal and replacement of the axle box, each shaft having at its end remote from its respective socket, a knob for rotating that shaft, the outer shaft passing through and hermetically engaging a stuffing box, connected to such stuffing box being a selectively operable valve for venting gas accumulated during the process of removing a defective axle box from the metering chamber, both inner and outer shafts being retractable into the stuffing box region of the tool so as to permit the closing of a gate valve between the stuffing box region and the base sealing unit of the tool, thus permitting removal of the shafts and the attached defective axle box from the tool and further permitting the replacement of a new axle box on the tool for a re-insertion in the metering chamber, the base sealing unit having transparent walls to assist in the process of orienting the shaft of a new axle box when it is being inserted in the metering chamber.

Element removal tool for system carrying fluid under pressure

To assist in locating an underground or otherwise hidden non-electrically-conducting plastic pipe carrying a fluid such as heating gas a tool is provided which comprises a reel of relatively stiff but flexible locator wire, a hermetically-sealing first bushing through which the locator wire passes and a coupler for engaging a pipe exposed to view but coupled to and communicating for fluid flow with the pipe to be located, such coupler being adapted to receive, in snug fashion, said first bushing and including a packing membrane through which said locator wire passes to further assure no loss of fluid from the pipe being located, said locator terminating at its extremity remote from the reel in a guide member having a shape which may be described as suggestive of an oblate spheroid; i.e., it is symmetrical about an axis aligned with the axis of the locator wire and has an equator from which it tapers downwardly in diameter towards two aligned ends; such guide member being inserted through the exposed pipe and into the pipe to be located, wherein it is pushed by means of the stiff locator wire until the terminus of pipe to be located is reached, whereupon appropriate signals are applied to such wire to permit the detection of the location of such wire and the plastic pipe, by appropriate signal sensing equipment. Alternatively, magnetometer detection equipment may be utilized to locate the locator wire.

Plastic-pipe locator tool

A nonvolatile static random access memory cell (10) includes a pair of cross-coupled transistors (12, 14) which function as a bistable circuit to store data states. Variable threshold transistors (36, 41) are respectively connected in series between the driver transistors (12, 14) and load devices (48, 50). A control node (40) is driven to a high voltage state to cause one of the variable threshold transistors (36, 41) to be driven to have a higher threshold voltage and thereby store the data state held in the cross-coupled transistors (12, 14). The data state is thus stored in nonvolatile form. Upon recall the memory cell (10) is reactivated and the threshold differential between the variable threshold transistors (36, 41) causes the driver transistors (12, 14) to be set at the stored data state. The data recalled by the memory cell (10) is in true rather than in complementary form. The variable threshold transistors (36, 41) are reset by driving the power terminal V.sub.cc to a high voltage state to reestablish common threshold voltages for the variable threshold voltage transistors (36, 41).

Nonvolatile static random access memory cell

In a memory array wherein each cell includes an emitter follower, a diode is formed on the emitter by a thin layer which is capable of being shorted by vertical migration of bit line atoms through the layer and into the emitter region. The thin layer is fabricated by epitaxially growing the thin layer over the wafer with the emitter diffusion aperture open, oxidizing the epitaxial layer, selectively removing portions of the polycrystalline epitaxial layer and removing the oxide from the remaining epitaxial layer in the emitter diffusion aperture.

Method of fabricating a vertical fuse utilizing epitaxial deposition and

An integrated circuit memory including a random memory (RAM) and a plurality of electrically alterable read only memories (EAROMS) having common controls. The data input for the RAM is either the system input or an EAROM and the data input for the EAROMS is only from the RAM. The system data output is from the RAM and the EAROMS.

Integrated RAM/EAROM memory system

An improved linear to digital translator having parallel current paths with unequal resistances. The resistances are sized according to a determined relationship between circuit parameters to improve crossover performance. In addition, non-saturating devices are used to reduce delay times.

Differential linear to digital translator

A bipolar device is formed in an N epitaxial layer region isolated from an N substrate and the remainder of the N epitaxial layer by a P surface ring and a buried P region. An N channel device is formed in the P surface ring and a P channel device is formed in the N epitaxial layer. A buried N region is formed in the buried P region using the same mask used to form the buried P region.

Method of making junction isolated bipolar device in unisolated IGFET IC

Vertical fuse and method of fabrication

A buffer having a first and second complementary IGFET input inverter connected in series and an output including a bipolar emitter follower with its base connected to the output of the first inverter, a second bipolar transistor connected in series with the emitter follower with its base connected to the output of the second inverter and an IGFET connected between the junction of the bipolar transistors and a voltage supply terminal and with its gate connected to the input of the first inverter. The output IGFET pulls the buffer output up to the supply voltage when the emitter of the emitter follower is at the supply voltage minus V.sub.BE.

Complementary IGFET buffer with improved bipolar output

Block redundancy is utilized to improve yield and lower die cost for an electrically programmable read only memory (EPROM). The EPROM is organized 8Kx8 with four primary memory blocks on each side of a central row decoder. Each block includes an array of memory cells, column select, column decode, sense amp, data buffer and other overhead circuitry. One block of redundant circuitry is also provided for each set of four blocks and includes a redundant memory matrix, a redundant column decoder, a redundant column select, a redundant sense amp and a redundant data buffer. Incorporated within each primary memory block is a multiplex logic circuit which is independently programmable to selectively disconnect the associated primary memory block and substitute the redundant memory block, including the redundant column decoder, column select, sense amp and data buffer. Each multiplex logic circuit includes a polysilicon fuse which is permanently programmable from a closed to an open circuit condition by applying a high voltage to the external data bit terminal which corresponds with the defective memory block cells. According to this arrangement, for each group of blocks, one out of four primary memory arrays including the associated column select, column decoder, sense amp and data buffer, may be replaced during wafer testing and after encapsulation.

Block redundancy for memory array

A memory array wherein each memory cell includes a resistive device which switches from a high to a low resistance state when a potential above its programmable threshold is applied and including a reference cell per word line having a reference switchable resistive device. Using a ramp addressing potential, the array output is disabled by an output disable circuit after a reference resistive device switches which is after the switching of an addressed low threshold resistive device cell and before the switching of an addressed high threshold resistive device cell.

Two switchable resistive element per cell memory array

A RAM cell having a pair of transistors formed in two adjacent wells laterally separated from each other and surrounded laterally by a common doped polycrystalline semiconductor moat. Dielectrical insulation separate the wells from the moat. The moat is discontinuous, forming thereby a pair of resistors connected together at one end and disconnected at the discontinuity. Surface contacts bridge adjacent areas of the well and the moat which are of the same conductivity type whereby the moat forms the load resistor for the transistor. Each transistor includes a second emitter. First level interconnects include a first interconnect interconnecting an emitter from each transistor, a second interconnect parallel to the first contacting the connected end of the moat resistors, a pair of interconnects each interconnecting the bridge contact of one transistor to the base of the other, and a pair of contacts for the other emitter regions. Second level interconnects include a pair of parallel interconnects connected to a respective emitter contact and orthogonal to the first interconnect. A method of fabrication is also described.

Fabrication of moat resistor ram cell utilizing polycrystalline

A memory array wherein each memory cell includes a pair of threshold resistive elements which switch from a high to a low resistance state when a potential above their respective programmable thresholds is applied. A binary value is stored by creating a threshold difference between the two resistive elements using two different value current sources. The binary value stored is read by applying a ramp potential and determining which threshold resistive element switched states first using a sense latch.

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Carrollton, TX, United States of America

David L Taylor